caideng.map.rpt

彩灯设计程序

+-----------------------------------------------+---+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 14    ;
; Number of registers using Synchronous Clear  ; 14    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 14    ;
; Number of synthesis-generated cells                    ; 16    ;
; Number of WYSIWYG LUTs                                 ; 14    ;
; Number of synthesis-generated LUTs                     ; 16    ;
; Number of WYSIWYG registers                            ; 14    ;
; Number of synthesis-generated registers                ; 0     ;
; Number of cells with combinational logic only          ; 16    ;
; Number of cells with registers only                    ; 0     ;
; Number of cells with combinational logic and registers ; 14    ;
+--------------------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                   ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+
; |caideng                               ; 30 (15)     ; 14           ; 0           ; 9    ; 16 (15)      ; 0 (0)             ; 14 (0)           ; 14 (0)          ; |caideng                                                           ;
;    |lpm_counter:\x1:a[0]_rtl_1|        ; 10 (0)      ; 10           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (0)           ; 10 (0)          ; |caideng|lpm_counter:\x1:a[0]_rtl_1                                ;
;       |alt_counter_f10ke:wysi_counter| ; 10 (10)     ; 10           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |caideng|lpm_counter:\x1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter ;
;    |lpm_counter:b_rtl_0|               ; 5 (0)       ; 4            ; 0           ; 0    ; 1 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |caideng|lpm_counter:b_rtl_0                                       ;
;       |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 4            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |caideng|lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter        ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/cd/caideng.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; caideng.vhd                      ; yes             ; G:/cd/caideng.vhd                                                   ;
; lpm_counter.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; alt_counter_f10ke.tdf            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf   ;
; flex10ke_lcell.inc               ; yes             ; c:/altera/quartus42/libraries/megafunctions/flex10ke_lcell.inc      ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 30      ;
; Total combinational functions     ; 30      ;
; Total 4-input functions           ; 10      ;
; Total 3-input functions           ; 2       ;
; Total 2-input functions           ; 7       ;
; Total 1-input functions           ; 11      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 14      ;
; Total logic cells in carry chains ; 14      ;
; I/O pins                          ; 9       ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 14      ;
; Total fan-out                     ; 105     ;
; Average fan-out                   ; 2.69    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Mar 18 21:47:03 2009
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off caideng -c caideng
Info: Found 2 design units, including 1 entities, in source file caideng.vhd
    Info: Found design unit 1: caideng-deng
    Info: Found entity 1: caideng
Warning: VHDL Process Statement warning at caideng.vhd(22): signal or variable "y" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "y" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "b[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: "\x1:a[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Implemented 39 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 8 output pins
    Info: Implemented 30 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Mar 18 21:47:06 2009
    Info: Elapsed time: 00:00:04