caideng.vhd

来自「彩灯设计程序」· VHDL 代码 · 共 34 行

entity caideng is
 port(clk:in bit;
      
      y:out bit_vector(7 downto 0));
end caideng;
architecture deng of caideng is
	 signal b:integer range 0 to 8;
begin 
   x1:process(clk)
     variable a:integer range 0 to 1000;
    
     begin 
       if clk'event and clk='1' and clk'last_value='0' then 
        if a<1000 then a:=a+1;
        else a:=0;
          if b<8 then b<=b+1;
		  else b<=0;
          end if;
        end if;
       end if;
   end process;
   x2:process(b)
      begin
        if b=0    then y<="00000001";
        elsif b=1 then y<="00000010";
        elsif b=2 then y<="00000100";
        elsif b=3 then y<="00001000";
        elsif b=4 then y<="00010000";
        elsif b=5 then y<="00100000";
        elsif b=6 then y<="01000000";
        elsif b=7 then y<="10000000";
        end if;
  end process;
end deng;