flash_prog.c

This is Bsl.zip for DSP c6000

/*******************************************************************************
* FILENAME
*   flash_prog.c
*
* DESCRIPTION
*   DSK flash programming - DSP Code
*
* REVISION HISTORY
*	Changed PAGE_SIZE to FLASH_WRITE_SIZE
*	Update of SDRAM configuration
*
*******************************************************************************/

#include <stdio.h>
#include <csl.h>
#include <csl_chip.h>
#include <csl_emif.h>
#include <bsl.h>
#include <bsl_flash.h>

#define PWD 0x12345678  
#define FLASH_WRITE_SIZE 0x80 


#pragma DATA_SECTION(host_buffer, "Host_Buffer")
  Uint32 host_buffer[33];
  Uint32 start_addr, prog_ptr, prog_flag, page_count, checksum, i;

/*-------------------------------------------------------------------------*/
/* main()                                                                  */
/*-------------------------------------------------------------------------*/

void main()
{
  /* Initialize the chip support library, required */
  CSL_init();
  /* Initialize the board support library, required */
  BSL_init();

  /* dsp and periphiral initialization */    
  CHIP_CSR_SET(0x100);                 /* Disable all interrupts              */
  CHIP_IER_SET(1);                     /* Disable all interrupts except NMI   */
  CHIP_ICR_SET(0xffff);                /* Clear all pending interrupts        */
 
/******************************************************************************\
 * CONFIGURE EMIF                                                             *
\******************************************************************************/  
  EMIF_configB(0x00003300,            /* EMIF global control register         */
               0xFFFFFF30,            /* CE0 - SDRAM                          */
               0xFFFFFF03,            /* CE1 - 8-bit asynch                   */
               0xFFFFFF23,            /* CE2 - 32-bit asynch on daughterboard */
               0xFFFFFF23,            /* CE3 - 32-bit asynch on daughterboard */
               0x07117000,            /* SDRAM control register (100 MHz)     */
               0x0000061A,            /* SDRAM Timing register                */
               0x00054519             /* SDRAM Extension register             */
              );

  host_buffer[0] = PWD;  /* send flag, indicating dsp is ready  */
  
  while(host_buffer[0] != 0);    /* wait host acknowledge  */
  start_addr = host_buffer[1];   /* save start programming address */
  prog_ptr = start_addr;         /* initialize pointer value   */
  page_count = 0;                /* initialize programmed page counter */
  prog_flag = 1;                 /* set prog_flag */

  while(prog_flag)               /* loop of receiving host data & program flash */
  {
     while (host_buffer[0] == 0); /* wait to receive a host packet data */
	 if (host_buffer[0] == 1)    /* check if last packet */
	 {
	   FLASH_write((Uint32)&host_buffer[1], prog_ptr, FLASH_WRITE_SIZE); /* prog a page of flash */
	   prog_ptr += FLASH_WRITE_SIZE;      /* update programming pointer */
	   page_count++;               /* increment the programmed page counter */
	   host_buffer[0] = 0;         /* send acknowledgement to host */  
	 }
	 else
	 {
	   prog_flag = 0;
	   host_buffer[0] = 0;
	 }
  } 
   
  checksum = 0;                  /* initialize checksum */
  checksum = FLASH_checksum(start_addr, page_count*FLASH_WRITE_SIZE);

  while ( host_buffer[0] == 0 );
  host_buffer[1] = checksum;
  host_buffer[0] = PWD;
  while(1);
}