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📄 bsl_led.asm

📁 This is Bsl.zip for DSP c6000
💻 ASM
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;******************************************************************************
;* TMS320C6x ANSI C Codegen                   Version 4.10 Beta (May  4 2001) *
;* Date/Time created: Tue May 29 12:12:02 2001                                *
;******************************************************************************

;******************************************************************************
;* GLOBAL FILE PARAMETERS                                                     *
;*                                                                            *
;*   Architecture      : TMS320C671x                                          *
;*   Optimization      : Enabled at level 3                                   *
;*   Optimizing for    : Speed                                                *
;*                       Based on options: -o3, no -ms                        *
;*   Endian            : Little                                               *
;*   Interrupt Thrshld : Disabled                                             *
;*   Memory Model      : Large                                                *
;*   Calls to RTS      : Far                                                  *
;*   Pipelining        : Enabled                                              *
;*   Speculative Load  : Disabled                                             *
;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
;*   Debug Info        : No Debug Info                                        *
;*                                                                            *
;******************************************************************************

	.asg	A15, FP
	.asg	B14, DP
	.asg	B15, SP
	.global	$bss


	.sect	".cinit"
	.align	8
	.field  	4,32
	.field  	_ledVal+0,32
	.field  	0,32			; _ledVal @ 0
	.sect	".text"
_ledVal:	.usect	.far,4,4

	.sect	".cinit"
	.align	8
	.field  	4,32
	.field  	_initialized$1+0,32
	.field  	0,32			; _initialized$1 @ 0
	.sect	".text"
_initialized$1:	.usect	.far,4,4
;	c:\ti\c6000\cgtools\bin\opt6x.exe -qq -v6711 -O3 C:\WINDOWS\TEMP\TI506495_2 C:\WINDOWS\TEMP\TI506495_4 
	.sect	".text:__LED_init"
	.clink
	.global	__LED_init

;******************************************************************************
;* FUNCTION NAME: __LED_init                                                  *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6,  *
;*                           B7,B8,B9,SP                                      *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6,  *
;*                           B7,B8,B9,SP                                      *
;*   Local Frame Size  : 0 Args + 0 Auto + 4 Save = 4 byte                    *
;******************************************************************************
__LED_init:
;** --------------------------------------------------------------------------*
           MVKL    .S2     _initialized$1,B5 ; |81| 
           MVKH    .S2     _initialized$1,B5 ; |81| 
           LDW     .D2T1   *B5,A1            ; |81| 
           MVKL    .S1     0x1800004,A0      ; |79| 
           MVKH    .S1     0x1800004,A0      ; |79| 
           LDW     .D1T2   *A0,B4            ; |79| 
           MVKL    .S2     0x1800004,B5      ; |85| 
   [ A1]   B       .S1     L5                ; |81| 
           MVK     .S1     240,A4            ; |86| 
           MVK     .S1     32,A3             ; |86| 
           CLR     .S2     B4,4,7,B6         ; |85| 

           MVKH    .S2     0x1800004,B5      ; |85| 
||         MVKL    .S1     0x1800004,A0      ; |86| 

           SET     .S2     B6,5,5,B6         ; |85| 
||         MVKH    .S1     0x1800004,A0      ; |86| 
||         STW     .D2T2   B3,*SP--(8)       ; |77| 

           ; BRANCH OCCURS                   ; |81| 
;** --------------------------------------------------------------------------*
           STW     .D2T2   B6,*B5            ; |85| 
           LDW     .D1T1   *A0,A0            ; |86| 
           NOP             4
           AND     .S1     A4,A0,A0          ; |86| 
           CMPEQ   .L1     A0,A3,A1          ; |86| 
   [ A1]   B       .S1     L4                ; |86| 
           MVK     .S1     0xf0,A5           ; |86| 

   [ A1]   MVKL    .S2     _ledVal,B5        ; |90| 
||         MVK     .S1     0x20,A4           ; |86| 

   [!A1]   MVKL    .S1     0x1800004,A3      ; (P) |86| 
   [!A1]   MVKH    .S1     0x1800004,A3      ; (P) |86| 
   [!A1]   LDW     .D1T1   *A3,A0            ; (P)  ^ |86| 
           ; BRANCH OCCURS                   ; |86| 
;** --------------------------------------------------------------------------*
           MVK     .S2     0x1,B0
           NOP             3
           AND     .S1     A5,A0,A3          ; (P)  ^ |86| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 86
;*      Loop opening brace source line : 0
;*      Loop closing brace source line : 0
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 8
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     1        0     
;*      .S units                     2*       1     
;*      .D units                     1        0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1        0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           1        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             2*       1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 8  Schedule found with 2 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 1
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
L1:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L2:    ; PIPED LOOP KERNEL

           CMPEQ   .L1     A3,A4,A1          ;  ^ |86| 
||         MVKL    .S1     0x1800004,A3      ; @|86| 

   [ A1]   ZERO    .D2     B0                ;  ^ 
||         MVKH    .S1     0x1800004,A3      ; @|86| 

   [ B0]   B       .S2     L2                ; |86| 
|| [ B0]   LDW     .D1T1   *A3,A0            ; @ ^ |86| 

           NOP             4
           AND     .S1     A5,A0,A3          ; @ ^ |86| 
;** --------------------------------------------------------------------------*
L3:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
           MVKL    .S2     _ledVal,B5        ; |90| 
;** --------------------------------------------------------------------------*
L4:    

           MVKH    .S2     _ledVal,B5        ; |90| 
||         ZERO    .D1     A0                ; |97| 
||         MVK     .S1     15,A3             ; |90| 

           STW     .D2T1   A3,*B5            ; |90| 
||         MVKH    .S1     0x90080000,A0     ; |97| 

           LDW     .D1T1   *A0,A0            ; |97| 
           ZERO    .D2     B5                ; |97| 
           MVKH    .S2     0x90080000,B5     ; |97| 
           NOP             2
           SET     .S1     A0,24,27,A0       ; |97| 
           STW     .D2T1   A0,*B5            ; |97| 
 NOP 9
 NOP 3
           MVKL    .S1     __BOARD_init,A0   ; |102| 
           MVKH    .S1     __BOARD_init,A0   ; |102| 
           B       .S2X    A0                ; |102| 
           MVKL    .S2     0x1800004,B5      ; |100| 
           MVKL    .S2     RL0,B3            ; |102| 
           MVKH    .S2     0x1800004,B5      ; |100| 
           STW     .D2T2   B4,*B5            ; |100| 
           MVKH    .S2     RL0,B3            ; |102| 
RL0:       ; CALL OCCURS                     ; |102| 
           MVKL    .S2     _initialized$1,B4 ; |103| 

           MVKH    .S2     _initialized$1,B4 ; |103| 
||         MVK     .S1     1,A0              ; |103| 

           STW     .D2T1   A0,*B4            ; |103| 
;** --------------------------------------------------------------------------*
L5:    
           LDW     .D2T2   *++SP(8),B3       ; |105| 
           NOP             4
           B       .S2     B3                ; |105| 
           NOP             5
           ; BRANCH OCCURS                   ; |105| 


	.sect	".text:_LED_toggle"
	.clink
	.global	_LED_toggle

;******************************************************************************
;* FUNCTION NAME: _LED_toggle                                                 *
;*                                                                            *
;*   Regs Modified     : A0,A1,A3,A4,A5,A6,A7,B0,B4,B5                        *
;*   Regs Used         : A0,A1,A3,A4,A5,A6,A7,B0,B3,B4,B5                     *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_LED_toggle:
;** --------------------------------------------------------------------------*
           MVKL    .S1     0x1800004,A0      ; |162| 
           MVKH    .S1     0x1800004,A0      ; |162| 
           LDW     .D1T1   *A0,A7            ; |162| 
           MVKL    .S2     0x1800004,B4      ; |166| 
           MVKL    .S2     0x1800004,B5      ; |167| 
           MVKH    .S2     0x1800004,B4      ; |166| 
           MVKH    .S2     0x1800004,B5      ; |167| 
           CLR     .S1     A7,4,7,A0         ; |166| 
           SET     .S1     A0,5,5,A0         ; |166| 
           STW     .D2T1   A0,*B4            ; |166| 
           LDW     .D2T2   *B5,B4            ; |167| 
           MVK     .S1     240,A0            ; |167| 
           MVK     .S1     32,A3             ; |167| 
           MV      .D1     A4,A6             ; |160| 
           MVK     .S1     0x20,A4           ; |167| 
           AND     .S2X    A0,B4,B4          ; |167| 
           CMPEQ   .L2X    B4,A3,B0          ; |167| 
   [ B0]   B       .S1     L9                ; |167| 
           MVK     .S1     0xf0,A5           ; |167| 
   [!B0]   MVKL    .S1     0x1800004,A3      ; (P) |167| 
   [!B0]   MVKH    .S1     0x1800004,A3      ; (P) |167| 
   [!B0]   LDW     .D1T1   *A3,A0            ; (P)  ^ |167| 
           NOP             1
           ; BRANCH OCCURS                   ; |167| 
;** --------------------------------------------------------------------------*
           MVK     .S2     0x1,B0
           NOP             3
           AND     .S1     A5,A0,A3          ; (P)  ^ |167| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 167
;*      Loop opening brace source line : 0
;*      Loop closing brace source line : 0
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 8
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     1        0     
;*      .S units                     2*       1     
;*      .D units                     1        0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1        0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           1        0     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             2*       1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 8  Schedule found with 2 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 1
;*      Prolog not removed
;*      Collapsed prolog stages     : 0
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
L6:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L7:    ; PIPED LOOP KERNEL

           CMPEQ   .L1     A3,A4,A1          ;  ^ |167| 
||         MVKL    .S1     0x1800004,A3      ; @|167| 

   [ A1]   ZERO    .D2     B0                ;  ^ 
||         MVKH    .S1     0x1800004,A3      ; @|167| 

   [ B0]   B       .S2     L7                ; |167| 
|| [ B0]   LDW     .D1T1   *A3,A0            ; @ ^ |167| 

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