bsl_dip.lst

This is Bsl.zip for DSP c6000

     107 00000008 02000266             LDW     .D1T2   *A0,B4            ; |87| 
     108 0000000c 0280022A             MVKL    .S2     0x1800004,B5      ; |92| 
     109 00000010 0300022A             MVKL    .S2     0x1800004,B6      ; |93| 
     110 00000014 0280C06A             MVKH    .S2     0x1800004,B5      ; |92| 
TMS320C6x COFF Assembler         Version 4.10 Beta (May  4 2001)     Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm                                                          PAGE    3

     111 00000018 0300C06A             MVKH    .S2     0x1800004,B6      ; |93| 
     112 0000001c 039087CA             CLR     .S2     B4,4,7,B7         ; |92| 
     113 00000020 039CA58A             SET     .S2     B7,5,5,B7         ; |92| 
     114 00000024 039402F6             STW     .D2T2   B7,*B5            ; |92| 
     115 00000028 029802E6             LDW     .D2T2   *B6,B5            ; |93| 
     116 0000002c 01807828             MVK     .S1     240,A3            ; |93| 
     117 00000030 00001028             MVK     .S1     32,A0             ; |93| 
     118 00000034 03100058             MV      .L1     A4,A6             ; |85| 
     119 00000038 02001028             MVK     .S1     0x20,A4           ; |93| 
     120 0000003c 01947F78             AND     .L1X    A3,B5,A3          ; |93| 
     121 00000040 00806A78             CMPEQ   .L1     A3,A0,A1          ; |93| 
     122 00000044 80000990     [ A1]   B       .S1     L5                ; |93| 
     123 00000048 02807828             MVK     .S1     0xf0,A5           ; |93| 
     124 0000004c 800008C0     [ A1]   ZERO    .D1     A0                ; |96| 
     125 00000050 91800228     [!A1]   MVKL    .S1     0x1800004,A3      ; (P) |93| 
     126 00000054 9180C068     [!A1]   MVKH    .S1     0x1800004,A3      ; (P) |93| 
     127 00000058 900C0264     [!A1]   LDW     .D1T1   *A3,A0            ; (P)  ^ |93| 
     128                               ; BRANCH OCCURS                   ; |93| 
     129                    ;** --------------------------------------------------------------------------*
     130 0000005c 000000AA             MVK     .S2     0x1,B0
     131 00000060 00004000             NOP             3
     132 00000064 0180A7E0             AND     .S1     A5,A0,A3          ; (P)  ^ |93| 
     133                    ;*----------------------------------------------------------------------------*
     134                    ;*   SOFTWARE PIPELINE INFORMATION
     135                    ;*
     136                    ;*      Loop source line               : 93
     137                    ;*      Loop opening brace source line : 0
     138                    ;*      Loop closing brace source line : 0
     139                    ;*      Known Minimum Trip Count         : 1
     140                    ;*      Known Max Trip Count Factor      : 1
     141                    ;*      Loop Carried Dependency Bound(^) : 8
     142                    ;*      Unpartitioned Resource Bound     : 2
     143                    ;*      Partitioned Resource Bound(*)    : 2
     144                    ;*      Resource Partition:
     145                    ;*                                A-side   B-side
     146                    ;*      .L units                     1        0     
     147                    ;*      .S units                     2*       1     
     148                    ;*      .D units                     1        0     
     149                    ;*      .M units                     0        0     
     150                    ;*      .X cross paths               0        0     
     151                    ;*      .T address paths             1        0     
     152                    ;*      Long read paths              0        0     
     153                    ;*      Long write paths             0        0     
     154                    ;*      Logical  ops (.LS)           1        0     (.L or .S unit)
     155                    ;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
     156                    ;*      Bound(.L .S .LS)             2*       1     
     157                    ;*      Bound(.L .S .D .LS .LSD)     2*       1     
     158                    ;*
     159                    ;*      Searching for software pipeline schedule at ...
     160                    ;*         ii = 8  Schedule found with 2 iterations in parallel
     161                    ;*      done
     162                    ;*
     163                    ;*      Loop is interruptible
     164                    ;*      Collapsed epilog stages     : 1
     165                    ;*      Prolog not removed
TMS320C6x COFF Assembler         Version 4.10 Beta (May  4 2001)     Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm                                                          PAGE    4

     166                    ;*      Collapsed prolog stages     : 0
     167                    ;*
     168                    ;*      Minimum required memory pad : 0 bytes
     169                    ;*
     170                    ;*      Minimum safe trip count     : 1
     171                    ;*----------------------------------------------------------------------------*
     172 00000068           L2:    ; PIPED LOOP PROLOG
     173                    ;** --------------------------------------------------------------------------*
     174 00000068           L3:    ; PIPED LOOP KERNEL
     175                    
     176 00000068 00906A79             CMPEQ   .L1     A3,A4,A1          ;  ^ |93| 
     177 0000006c 01800228  ||         MVKL    .S1     0x1800004,A3      ; @|93| 
     178                    
     179 00000070 800428C3     [ A1]   ZERO    .D2     B0                ;  ^ 
     180 00000074 0180C068  ||         MVKH    .S1     0x1800004,A3      ; @|93| 
     181                    
     182 00000078 20000113     [ B0]   B       .S2     L3                ; |93| 
     183 0000007c 200C0264  || [ B0]   LDW     .D1T1   *A3,A0            ; @ ^ |93| 
     184                    
     185 00000080 00006000             NOP             4
     186 00000084 0180A7E0             AND     .S1     A5,A0,A3          ; @ ^ |93| 
     187                    ;** --------------------------------------------------------------------------*
     188 00000088           L4:    ; PIPED LOOP EPILOG
     189                    ;** --------------------------------------------------------------------------*
     190 00000088 000008C0             ZERO    .D1     A0                ; |96| 
     191                    ;** --------------------------------------------------------------------------*
     192 0000008c           L5:    
     193 0000008c 00480468             MVKH    .S1     0x90080000,A0     ; |96| 
     194 00000090 00800264             LDW     .D1T1   *A0,A1            ; |96| 
     195 00000094 0280022A             MVKL    .S2     0x1800004,B5      ; |100| 
     196 00000098 0280C06A             MVKH    .S2     0x1800004,B5      ; |100| 
     197 0000009c 000C0362             B       .S2     B3                ; |103| 
     198 000000a0 021402F6             STW     .D2T2   B4,*B5            ; |100| 
     199 000000a4 000709A0             SHRU    .S1     A1,24,A0          ; |97| 
     200 000000a8 0080C7E0             AND     .S1     A6,A0,A1          ; |97| 
     201 000000ac 808000A8     [ A1]   MVK     .S1     0x1,A1            ; |98| 
     202 000000b0 02040940             MV      .D1     A1,A4             ; |102| 
     203                               ; BRANCH OCCURS                   ; |103| 
     204                    
     205                    
     206                    ;******************************************************************************
     207                    ;* UNDEFINED EXTERNAL REFERENCES                                              *
     208                    ;******************************************************************************
     209                            .global __BOARD_init

No Assembly Errors, No Assembly Warnings