ata-r32.txt

ATA光驱的接口标准, 对于了解光驱的原理很有帮助。

 - If CSEL is open then the drive address is 1

Special cabling can be used by the system manufacturer to selectively ground 
CSEL e.g. CSEL of Drive 0 is connected to the CSEL conductor in the cable, and 
is grounded, thus allowing the drive to recognize itself as Drive 0. CSEL of 
Drive 1 is not connected to CSEL because the conductor is removed, thus the 
drive can recognize itself as Drive 1. 

              ______ CSEL Conductor _________________________      
             |                            |                Open
             |Ground                      |                  | 
          +------+                   +---------+        +---------+
          | Host |                   | Drive 0 |        | Drive 1 |
          +------+                   +---------+        +---------+

              ______ CSEL Conductor _________________________
             |                          Open                 |  
             |Ground                      |                  |
          +------+                   +---------+        +---------+
          | Host |                   | Drive 1 |        | Drive 0 |
          +------+                   +---------+        +---------+

                          FIGURE 6-1:  Cable Select 

7.  Logical Interface 

7.1  General 

7.1.1  Bit Conventions

Bit names are shown in all upper case letters except where a lower case n 
precedes a bit name. This indicates that when nBIT=0 (bit is zero) the action 
is true and when nBIT=1 (bit is one) the action is false. If there is no 
preceding n, then when BIT=1 it is true, and when BIT=0 it is false. 

A bit can be set to one or cleared to zero and polarity influences whether it 
is to be interpreted as true or false:

          True      BIT=1       nBIT=0 
          False     BIT=0       nBIT=1 

7.1.2  Environment

The drives using this interface shall be programmed by the host computer to 
perform commands and return status to the host at command completion. When two 
drives are daisy chained on the interface, commands are written in parallel to 
both drives, and for all except the Execute Diagnostics command, only the 
selected drive executes the command. On an Execute Diagnostics command 
addressed to Drive 0, both drives shall execute the command, and Drive 1 shall 
post its status to Drive 0 via PDIAG-.

Drives are selected by the DRV bit in the Drive/Head Register (see 7.2.8), and 
by a jumper or switch on the drive designating it as either a Drive 0 or as 
Drive 1. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected. 
When drives are daisy chained, one shall be set as Drive 0 and the other as 
Drive 1. When a single drive is attached to the interface it shall be set as 
Drive 0. 

Prior to the adoption of this standard, some drives may have provided jumpers 
to indicate Drive 0 with no Drive 1 present, or Drive 0 with Drive 1 present.

Throughout this document, drive selection always refers to the state of the 
DRV bit, the position of the Drive 0/Drive 1 jumper or switch, or use of the 
CSEL pin. 

A drive can operate in either of two addressing modes, CHS or LBA, on a 
command by command basis. A drive which can support LBA mode indicates this in 
the Identify Drive Information. If the host selects LBA mode in the Drive/Head 
register, Sector Number, Cylinder Low, Cylinder High and HS3-HS0 of the 
Drive/Head Register contains the zero based-LBA.

In LBA mode, the sectors on the drive are assumed to be linearly mapped with 
an Inital definition of:

        LBA 0 = Cylinder 0/Head 0/Sector 1.

Irrespective of translate mode geometry set by the host, the LBA address of a 
given sector does not change:

  LBA = [ (Cylinder * No of Heads + Heads) * Sectors/Track ] + (Sector-1) 

7.2  I/O Register Descriptions 

Communication to or from the drive is through an I/O Register that routes the 
input or output data to or from registers (selected) by a code on signals from 
the host (CS1FX-, CS3FX-, DA2, DA1, DA0, DIOR- and DIOW-). 

The Command Block Registers are used for sending commands to the drive or 
posting status from the drive. 

The Control Block Registers are used for drive control and to post alternate 
status. 

Table 7-1 lists these registers and the addresses that select them. 

Logic conventions are:   A = signal asserted
                         N = signal negated
                         x = does not matter which it is

            TABLE 7-1:  I/O PORT FUNCTIONS/SELECTION ADDRESSES 
 +-------------------------------+-----------------------------------------+
 |         Addresses             |                 Functions               |
 |CS1FX-|CS3FX-| DA2 | DA1 | DA0 |    READ (DIOR-)     |   WRITE (DIOW-)   |
 +------+------+-----+-----+-----+---------------------+-------------------+
 |                                        Control Block Registers          |
 +------+------+-----+-----+-----+---------------------+-------------------+
 |  N   |  N   |  x  |  x  |  x  | Data Bus High Imped | Not used          |
 |  N   |  A   |  0  |  x  |  X  | Data Bus High Imped | Not used          |
 |  N   |  A   |  1  |  0  |  x  | Data Bus High Imped | Not used          |
 |  N   |  A   |  1  |  1  |  0  | Alternate Status    | Device Control    | 
 |  N   |  A   |  1  |  1  |  1  | Drive Address       | Not used          |
 +------+------+-----+-----+-----+---------------------+-------------------+
 |                                        Command Block Registers          |
 +------+------+-----+-----+-----+---------------------+-------------------+
 |  A   |  N   |  0  |  0  |  0  | Data                | Data              |
 |  A   |  N   |  0  |  0  |  1  | Error Register      | Features          |
 |  A   |  N   |  0  |  1  |  0  | Sector Count        | Sector Count      |
 |  A   |  N   |  0  |  1  |  1  | Sector Number       | Sector Number     | 
 |  A   |  N   |  0  |  1  |  1  | * LBA Bits  0- 7    | * LBA Bits  0- 7  |
 |  A   |  N   |  1  |  0  |  0  | Cylinder Low        | Cylinder Low      |
 |  A   |  N   |  1  |  0  |  0  | * LBA Bits  8-15    | * LBA Bits  8-15  |
 |  A   |  N   |  1  |  0  |  1  | Cylinder High       | Cylinder High     | 
 |  A   |  N   |  1  |  0  |  1  | * LBA Bits 16-23    | * LBA Bits 16-23  |
 |  A   |  N   |  1  |  1  |  0  | Drive/Head          | Drive/Head        |
 |  A   |  N   |  1  |  1  |  0  | * LBA Bits 24-27    | * LBA Bits 24-27  |
 |  A   |  N   |  1  |  1  |  1  | Status              | Command           |
 |  A   |  A   |  x  |  x  |  x  | Invalid Address     | Invalid Address   |
 +------+------+-----+-----+-----+---------------------+-------------------+
                      * Mapping of registers in LBA Mode

7.2.1  Alternate Status Register

This register contains the same information as the Status Register in the 
command block. The only difference being that reading this register does not 
imply interrupt acknowledge or clear a pending interrupt. 

         7       6       5       4       3       2       1       0 
     +-------+-------+-------+-------+-------+-------+-------+-------+
     |  BSY  | DRDY  |  DWF  |  DSC  |  DRQ  | CORR  |  IDX  |  ERR  | 
     +-------+-------+-------+-------+-------+-------+-------+-------+

See 7.2.13 for definitions of the bits in this register. 

7.2.2  Command Register 

This register contains the command code being sent to the drive. Command 
execution begins immediately after this register is written. The executable 
commands, the command codes, and the necessary parameters for each command are 
listed in Table 9-1.

7.2.3  Cylinder High Register

This register contains the high order bits of the starting cylinder address 
for any disk access. At the end of the command, this register is updated to 
reflect the current cylinder number. The most significant bits of the cylinder 
address shall be loaded into the cylinder high Register. 

In LBA Mode this register contains Bits 16-23. At the end of the command, this 
register is updated to reflect the current LBA Bits 16-23.

  NOTE: Prior to the introduction of this standard, only the lower 2 bits of 
        this register were valid, limiting cylinder address to 10 bits i.e. 
        1,024 cylinders.

7.2.4  Cylinder Low Register

This register contains the low order 8 bits of the starting cylinder address 
for any disk access. At the end of the command, this register is updated to 
reflect the current cylinder number. 

In LBA Mode this register contains Bits 8-15. At the end of the command, this 
register is updated to reflect the current LBA Bits 8-15.

7.2.5  Data Register

This 16-bit register is used to transfer data blocks between the device data 
buffer and the host. It is also the register through which sector information 
is transferred on a Format Track command. Data transfers may be either PIO or 
DMA. 

7.2.6  Device Control Register

The bits in this register are as follows: 

         7       6       5       4       3       2       1       0 
     +-------+-------+-------+-------+-------+-------+-------+-------+
     |   x   |   x   |   x   |   x   |   1   | SRST  |  nIEN |   0   | 
     +-------+-------+-------+-------+-------+-------+-------+-------+

 - SRST is the host software reset bit. The drive is held reset when this bit 
   is set. If two disk drives are daisy chained on the interface, this bit 
   resets both simultaneously. Drive 1 is not required to execute the DASP- 
   handshake procedure.
 - nIEN is the enable bit for the drive interrupt to the host. When nIEN=0, 
   and the drive is selected, INTRQ shall be enabled through a tri-state 
   buffer. When nIEN=1, or the drive is not selected, the INTRQ signal shall 
   be in a high impedance state. 

7.2.7  Drive Address Register

This register contains the inverted drive select and head select addresses of 
the currently selected drive. The bits in this register are as follows: 

         7       6       5       4       3       2       1       0 
     +-------+-------+-------+-------+-------+-------+-------+-------+
     |  HiZ  |  nWTG |  nHS3 |  nHS2 |  nHS1 |  nHS0 |  nDS1 |  nDS0 | 
     +-------+-------+-------+-------+-------+-------+-------+-------+

 - HiZ shall always be in a high impedance state. 
 - nWTG is the Write Gate bit. When writing to the disk drive is in progress, 
   nWTG=0.
 - nHS3 through nHS0 are the one's complement of the binary coded address of 
   the currently selected head. For example, if nHS3 through nHS0 are 1100b, 
   respectively, head 3 is selected. nHS3 is the most significant bit. 
 - nDS1 is the drive select bit for drive 1. When drive 1 is selected and 
   active, nDS1=0. 
 - nDS0 is the drive select bit for drive 0. When drive 0 is selected and 
   active, nDS0=0.

  NOTE: Care should be used when interpreting these bits, as they do not 
        always represent the expected status of drive operations at the 
        instant the status was put into this register. This is because of the 
        use of cacheing, translate mode and the Drive 0/Drive 1 concept with 
        each drive having its own embedded controller. 

7.2.8  Drive/Head Register

This register contains the drive and head numbers. The contents of this 
register define the number of heads minus 1, when executing an Initialize 
Drive Parameters command. 

         7       6       5       4       3       2       1       0 
     +-------+-------+-------+-------+-------+-------+-------+-------+
     |   1   |   L   |   1   |  DRV  |  HS3  |  HS2  |  HS1  |  HS0  | 
     +-------+-------+-------+-------+-------+-------+-------+-------+

 - L is the binary encoded address mode select. When L=0, addressing is by CHS 
   mode. When L=1, addressing is by LBA mode. 
 - DRV is the binary encoded drive select number. When DRV=0, Drive 0 is 
   selected. When DRV=1, Drive 1 is selected.
 - If L=0, HS3 through HS0 contain the binary coded address of the head to be 
   selected e.g. if HS3 through HS0 are 0011b, respectively, head 3 will be 
   selected. HS3 is the most significant bit. At command completion, these 
   bits are updated to reflect the currently selected head. 
   If L=1, HS3 through HS0 contain bits 24-27 of the LBA. At command 
   completion, these bits are updated to reflect the current LBA bits 24-27. 

7.2.9  Error Register 

This register contains status from the last command executed by the drive or a 
Diagnostic Code. 

At the completion of any command except Execute Drive Diagnostic, the contents 
of this register are valid when ERR=1 in the Status Register. 

Following a power on, a reset, or completion of an Execute Drive Diagnostic 
command, this register contains a Diagnostic Code (see Table 9-2). 

         7       6       5       4       3       2       1       0 
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