📄 ata-r32.txt
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| HOST |
| |
+------+====== AT Bus ======+-------------------------+
| |
| ADAPTER |
| |
+--------^-----------+
| ATA Interface
| _____________________
|/ |
+------v--+ +------v--+
| DRIVE 0 | | DRIVE 1 |
+---------+ +---------+
FIGURE 5-2: HOST BUS ADAPTER AND PERIPHERAL DEVICES
+-----------------------------------------------------+
| |
| HOST |
| |
+---------------^-------------------------------------+
| ATA Interface
+------v-----+
| |
| CONTROLLER |
| |
+-^----^---^-+
| | |__________________ Device Interface
| ___|_________________ | e.g. ESDI, SCSI
|/ | | |
+-v----v--+ +-v----v--+
| DRIVE | | DRIVE |
+---------+ +---------+
FIGURE 5-3: ATA INTERFACE TO CONTROLLER AND PERIPHERAL DEVICES
5.2 Addressing Considerations
In traditional controller operation, only the selected controller receives
commands from the host following selection. In this standard, the register
contents go to both drives (and their embedded controllers). The host
discriminates between the two by using the DRV bit in the Drive/Head Register.
5.3 DC Cable and Connector
The drive receives DC power through a 4-pin or a low-power application 3-pin
connector.
A drive designed for 3.3V applications may be plugged into a receptacle
designed to accept a drive designed for 5V applications, with 12V lines for
additional power. It is not required that the drive operate, but it is
recommended that precautions be taken to prevent damage to the drive.
A drive designed for 5V applications may be plugged into a receptacle designed
to accept a drive designed for 3.3V applications, with 5V lines for additional
power. It is not anticipated that damage could occur to the drive, but it is
likely to fail in an undetermined manner.
5.3.1 4-Pin Power
The pin assignments are shown in Table 5-1. Recommended part numbers for the
mating connector to 18AWG cable are shown below, but equivalent parts may be
used.
Connector (4 Pin) AMP 1-480424-0 or equivalent.
Contacts (Loose Piece) AMP 60619-4 or equivalent.
Contacts (Strip) AMP 61117-4 or equivalent.
TABLE 5-1: DC INTERFACE
+------------------------+------------+
| POWER LINE DESIGNATION | PIN NUMBER |
+------------------------+------------+
| +12V | 1-01 |
| +12V RETURN | 1-02 |
| +5V RETURN | 1-03 |
| +5V | 1-04 |
+------------------------+------------+
5.3.2 3-Pin Power
The pin assignments are shown in Table 5-2. Recommended part numbers for the
mating connector to 18AWG cable are shown below, but equivalent parts may be
used.
Connector (3 Pin) Molex 5484 39-27-0032 or equivalent.
TABLE 5-2: DC INTERFACE
+------------------------+------------+
| POWER LINE DESIGNATION | PIN NUMBER |
+------------+-----------+------------+
| +5V | +3.3V | 1-01 |
| +12V | +5V | 1-02 |
| Ground | Ground | 1-03 |
+------------+-----------+------------+
5.3.3 Device Grounding
System ground may be connected to a "quick-connect" terminal equivalent to:
Drive Connector Terminal AMP 61664-1 or equivalent.
Cable Connector Terminal AMP 62137-2 or equivalent.
Provision for tying the DC Logic ground and the chassis ground together or for
separating these two ground planes is vendor specific.
5.4 I/O Connector
The I/O connector is a 40-pin connector as shown in Figure 5-4, with pin
assignments as shown in Table 6-1.
The connector should be keyed to prevent the possibility of installing it
upside down. A key is provided by the removal of Pin 20. The corresponding pin
on the cable connector should be plugged.
The pin locations are governed by the cable plug, not the receptacle. The way
in which the receptacle is mounted on the Printed Circuit Board affects the
pin positions, and pin 1 should remain in the same relative position. This
means the pin numbers of the receptacle may not reflect the conductor number
of the plug. The header receptacle is not polarized, and all the signals are
relative to Pin 20, which is keyed.
By using the plug positions as primary, a straight cable can connect drives.
As shown in Figure 5-4, conductor 1 on pin 1 of the plug has to be in the
same relative position no matter what the receptacle numbering looks like.
If receptacle numbering was followed, the cable would have to twist 180
degrees between a drive with top-mounted receptacles, and a drive with
bottom-mounted receptacles.
+-----------------------+
| 1|
|40 20 2|
==+==== Circuit Board ====+== ==+==== Circuit Board ====+==
| 1|
|40 20 2|
+-----------------------+
FIGURE 5-4: 40-PIN CONNECTOR MOUNTING
Recommended part numbers for the mating connector are shown below, but
equivalent parts may be used.
Connector (40 Pin) 3M 3417-7000 or equivalent.
Strain relief 3M 3448-2040 or equivalent.
Flat Cable (Stranded 28 AWG) 3M 3365-40 or equivalent.
Flat Cable (Stranded 28 AWG) 3M 3517-40 (Shielded) or equivalent.
5.5 I/O Cable
The cable specifications affect system integrity and the maximum length that
can be supported in any application.
TABLE 5-3: CABLE PARAMETERS
+--------------------------------------------+------+--------+
| Cable length of 0.46m (18 inches) * | Min | Max |
+--------------------------------------------+------+--------+
| Driver IoL Sink Current for 5V operation | 12mA | |
| Driver IoL Sink Current for 3.3V operation | 8mA | |
| Driver IoH Source Current | | -400uA |
| Cable Capacitive Loading | | 200pF |
+--------------------------------------------+------+--------+
* This distance may be exceeded in circumstances where the
characteristics of both ends of the cable can be controlled.
6. Physical Interface
6.1 Signal Conventions
Signal names are shown in all upper case letters. Signals can be asserted
(active, true) in either a high (more positive voltage) or low (less positive
voltage) state. A dash character (-) at the beginning or end of a signal name
indicates it is asserted at the low level (active low). No dash or a plus
character (+) at the beginning or end of a signal name indicates it is
asserted high (active high). An asserted signal may be driven high or low by
an active circuit, or it may be allowed to be pulled to the correct state by
the bias circuitry.
Control signals that are asserted for one function when high and asserted for
another function when low are named with the asserted high function name
followed by a slash character (/), and the asserted low function name followed
with a dash (-) e.g. BITENA/BITCLR- enables a bit when high and clears a bit
when low. All signals are TTL compatible unless otherwise noted. Negated means
that the signal is driven by an active circuit to the state opposite to the
asserted state (inactive, or false) or may be simply released (in which case
the bias circuitry pulls it inactive, or false), at the option of the
implementor.
Control signals that may be used for two mutually exclusive functions are
identified with their two names separated by a colon e.g. SPSYNC:CSEL can be
used for either the Spindle Sync or the Cable Select functions.
6.2 Signal Summary
The physical interface consists of single ended TTL compatible receivers and
drivers communicating through a 40-conductor flat ribbon nonshielded cable
using an asynchronous interface protocol. The pin numbers and signal names
are shown in Table 6-1. Reserved signals shall be left unconnected.
TABLE 6-1: INTERFACE SIGNALS
+----------------------------------+ +-----------+
| HOST I/O | | DRIVE I/O |
| CONNECTOR | | CONNECTOR |
| | | |
| HOST RESET 1 | ----- RESET- -------->| 1 |
| 2 | ----- Ground -------- | 2 |
| HOST DATA BUS BIT 7 3 |<----- DD7 ----------->| 3 |
| HOST DATA BUS BIT 8 4 |<----- DD8 ----------->| 4 |
| HOST DATA BUS BIT 6 5 |<----- DD6 ----------->| 5 |
| HOST DATA BUS BIT 9 6 |<----- DD9 ----------->| 6 |
| HOST DATA BUS BIT 5 7 |<----- DD5 ----------->| 7 |
| HOST DATA BUS BIT 10 8 |<----- DD10 ---------->| 8 |
| HOST DATA BUS BIT 4 9 |<----- DD4 ----------->| 9 |
| HOST DATA BUS BIT 11 10 |<----- DD11 ---------->| 10 |
| HOST DATA BUS BIT 3 11 |<----- DD3 ----------->| 11 |
| HOST DATA BUS BIT 12 12 |<----- DD12 ---------->| 12 |
| HOST DATA BUS BIT 2 13 |<----- DD2 ----------->| 13 |
| HOST DATA BUS BIT 13 14 |<----- DD13 ---------->| 14 |
| HOST DATA BUS BIT 1 15 |<----- DD1 ----------->| 15 |
| HOST DATA BUS BIT 14 16 |<----- DD14 ---------->| 16 |
| HOST DATA BUS BIT 0 17 |<----- DD0 ----------->| 17 |
| HOST DATA BUS BIT 15 18 |<----- DD15 ---------->| 18 |
| 19 | ----- Ground -------- | 19 |
| 20 | ----- (keypin) ------ | 20 |
| DMA REQUEST 21 |<----- DMARQ --------- | 21 |
| 22 | ----- Ground -------- | 22 |
| HOST I/O WRITE 23 | ----- DIOW- --------->| 23 |
| 24 | ----- Ground -------- | 24 |
| HOST I/O READ 25 | ----- DIOR- --------->| 25 |
| 26 | ----- Ground -------- | 26 |
| I/O CHANNEL READY 27 |<----- IORDY --------- | 27 |
| SPINDLE SYNC or CABLE SELECT 28 |*---- SPSYNC:CSEL -----*| 28 |
| DMA ACKNOWLEDGE 29 | ----- DMACK- -------->| 29 |
| 30 | ----- Ground -------- | 30 |
| HOST INTERRUPT REQUEST 31 |<----- INTRQ --------- | 31 |
| HOST 16 BIT I/O 32 |<----- IOCS16- ------- | 32 |
| HOST ADDRESS BUS BIT 1 33 | ----- DA1 ----------->| 33 |
| PASSED DIAGNOSTICS 34 |*----- PDIAG- --------*| 34 |
| HOST ADDRESS BUS BIT 0 35 | ----- DAO ----------->| 35 |
| HOST ADDRESS BUS BIT 2 36 | ----- DA2 ----------->| 36 |
| HOST CHIP SELECT 0 37 | ----- CS1FX- -------->| 37 |
| HOST CHIP SELECT 1 38 | ----- CS3FX- -------->| 38 |
| DRIVE ACTIVE/DRIVE 1 PRESENT 39 |<----- DASP- ---------*| 39 |
| 40 | ----- Ground -------- | 40 |
+----------------------------------+ +-----------+
* Drive Intercommunication Signals
+---HOST---+ +-Drive 0-+ +-Drive 1-+
| 28 | ----->| 28 28 |<-- SPSYNC:CSEL -->| 28 |
| 34 | ----- | 34 34 |<----- PDIAG- ---- | 34 |
| 39 |<----- | 39 39 |<----- DASP- ----- | 39 |
+----------+ +---------+ +---------+
6.3 Signal Descriptions
The interface signals and pins are described in more detail than shown in
Table 6-1. The signals are listed according to function, rather than in
numerical connector pin order. Table 6-2 lists signal name mnemonic, connector
pin number, whether input to (I) or output from (O) the drive, and full signal
name.
TABLE 6-2: INTERFACE SIGNALS DESCRIPTION
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