📄 ata-r32.txt
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9.9.17 Word 59: Multiple Sector Setting 31
9.9.18 Word 60-61: Total Number of User Addressable Sectors 31
9.9.19 Word 62: Single Word DMA Transfer 31
9.9.20 Word 63: Multiword DMA Transfer 31
9.10 Idle 31
9.11 Idle Immediate 32
9.12 Initialize Drive Parameters 32
9.13 NOP 32
9.14 Read Buffer 32
9.15 Read DMA 33
9.16 Read Long 33
9.17 Read Multiple Command 33
9.18 Read Sector(s) 34
9.19 Read Verify Sector(s) 34
9.20 Recalibrate 35
9.21 Seek 35
9.22 Set Features 35
9.23 Set Multiple Mode 36
9.24 Sleep 36
9.25 Standby 37
9.26 Standby Immediate 37
9.27 Write Buffer 37
9.28 Write DMA 37
9.29 Write Long 37
9.30 Write Multiple Command 38
9.31 Write Same 38
9.32 Write Sector(s) 39
9.33 Write Verify 39
10. Protocol Overview 39
10.1 PIO Data In Commands 40
10.1.1 PIO Read Command 40
10.1.2 PIO Read Aborted Command 40
10.2 PIO Data Out Commands 40
10.2.1 PIO Write Command 41
10.2.2 PIO Write Aborted Command 41
10.3 Non-Data Commands 41
10.4 Miscellaneous Commands 42
10.5 DMA Data Transfer Commands (Optional) 42
10.5.1 Normal DMA Transfer 43
10.5.2 Aborted DMA Transfer 43
10.5.3 Aborted DMA Command 43
11. Timing 43
11.1 Deskewing 43
11.2 Symbols 43
11.3 Terms 44
11.4 Data Transfers 45
11.5 Power On and Hard Reset 48
FIGURES
FIGURE 5-1: ATA INTERFACE TO EMBEDDED BUS PERIPHERALS 4
FIGURE 5-2: HOST BUS ADAPTER AND PERIPHERAL DEVICES 4
FIGURE 5-3: ATA INTERFACE TO CONTROLLER AND PERIPHERAL DEVICES 4
FIGURE 5-4: 40-PIN CONNECTOR MOUNTING 6
FIGURE 6-1: Cable Select 14
FIGURE 11-1: PIO DATA TRANSFER TO/FROM DRIVE 45
FIGURE 11-2: IORDY TIMING REQUIREMENTS 46
FIGURE 11-3: SINGLE WORD DMA DATA TRANSFER 46
FIGURE 11-4: MULTIWORD DMA DATA TRANSFER 47
FIGURE 11-5: RESET SEQUENCE 48
TABLES
TABLE 5-1: DC INTERFACE 5
TABLE 5-2: DC INTERFACE 5
TABLE 5-3: CABLE PARAMETERS 7
TABLE 6-1: INTERFACE SIGNALS 8
TABLE 6-2: INTERFACE SIGNALS DESCRIPTION 9
TABLE 7-1: I/O PORT FUNCTIONS/SELECTION ADDRESSES 16
TABLE 8-1: POWER CONDITIONS 22
TABLE 8-2: REGISTER CONTENTS 23
TABLE 9-1: COMMAND CODES AND PARAMETERS - Part 1 of 2 24
TABLE 9-1: COMMAND CODES AND PARAMETERS - Part 2 of 2 25
TABLE 9-2: DIAGNOSTIC CODES 27
TABLE 9-4: SET FEATURE REGISTER DEFINITIONS 35
TABLE C-1 SIGNAL ASSIGNMENTS FOR ATA 58
Information Processing Systems --
AT Attachment Interface
1. Scope
This standard defines the AT Attachment Interface.
The CAM Committee was formed in October, 1988 and the first working document
of the AT Attachment was introduced in March, 1989.
1.1 Description of Clauses
Clause 1 contains the Scope and Purpose.
Clause 2 contains Referenced and Related International Standards.
Clause 3 contains the General Description.
Clause 4 contains the Glossary.
Clause 5 contains the electrical and mechanical characteristics; covering the
interface cabling requirements of the DC, data cables and connectors.
Clause 6 contains the signal descriptions of the AT Attachment Interface.
Clause 7 contains descriptions of the registers of the AT Attachment
Interface.
Clause 8 describes the programming requirements of the AT Attachment
Interface.
Clause 9 contains descriptions of the commands of the AT Attachment Interface.
Clause 10 contains an overview of the protocol of the AT Attachment Interface.
Clause 11 contains the interface timing diagrams.
Annex A is informative.
Annex B is informative.
Annex C is informative.
2. References
None.
3. General Description
The application environment for the AT Attachment Interface is any computer
which uses an AT Bus or 40-pin ATA interface.
The PC AT Bus (tm) is a widely used and implemented interface for which a
variety of peripherals have been manufactured. As a means of reducing size and
cost, a class of products has emerged which embed the controller functionality
in the drive. These new products utilize the AT Bus fixed disk interface
protocol, and a subset of the AT bus. Because of their compatibility with
existing AT hardware and software this interface quickly became a de facto
industry standard.
The purpose of the ATA standard is to define the de facto implementations.
Software in the Operating System dispatches I/O (Input/Output) requests via
the AT Bus to peripherals which respond to direct commands.
3.1 Structure
This standard relies upon specifications of the mechanical and electrical
characteristics of the AT Bus and a subset of the AT Bus specifically
developed for the direct attachment of peripherals.
Also defined are the methods by which commands are directed to peripherals,
the contents of registers and the method of data transfers.
4. Definitions and Conventions
4.1 Definitions
For the purpose of this standard the following definitions apply:
4.1.1 ATA (AT Attachment): ATA defines a compatible register set and a 40-pin
connector and its associated signals.
4.1.2 CHS (Cylinder-Head-Sector): This term defines the addressing mode of the
drive as being by physical address.
4.1.3 Data block: This term describes a data transfer, and is typically a
single sector, except when declared otherwise by use of the Set Multiple
command.
4.1.4 DMA (Direct Memory Access): A means of data transfer between
peripheral and host memory without processor intervention.
4.1.5 LBA (Logical Block Address): This term defines the addressing mode of
the drive as being by the linear mapping of sectors from 1 to n.
4.1.6 Optional: This term describes features which are not required by the
standard. However, if any feature defined by the standard is implemented, it
shall be done in the same way as defined by the standard. Describing a feature
as optional in the text is done to assist the reader. If there is a conflict
between text and tables on a feature described as optional, the table shall be
accepted as being correct.
4.1.7 PIO (Programmed Input/Output): A means of data transfer that requires
the use of the host processor.
4.1.8 Reserved: Where this term is used for bits, bytes and fields; the bits,
bytes and fields are set aside for future standardization, and shall be zero.
4.1.9 VU (Vendor Unique): This term is used to describe bits, bytes,
fields, code values and features which are not described in this standard,
and may be used in a way that varies between vendors.
4.2 Conventions
Certain terms used herein are the proper names of signals. These are printed
in uppercase to avoid possible confusion with other uses of the same words;
e.g., ATTENTION. Any lowercase uses of these words have the normal American-
English meaning.
A number of conditions, commands, sequence parameters, events, English text,
states or similar terms are printed with the first letter of each word in
uppercase and the rest lowercase; e.g., In, Out, Request Status. Any lowercase
uses of these words have the normal American-English meaning.
The American convention of numbering is used i.e., the thousands and higher
multiples are separated by a comma and a period is used as the decimal point.
This is equivalent to the ISO convention of a space and comma.
American: 0.6 ISO: 0,6
1,000 1 000
1,323,462.9 1 323 462,9
5. Interface Cabling Requirements
5.1 Configuration
This standard provides the capability of operating on the AT Bus in a daisy
chained configuration with a second drive that operates in accordance with
these standards. One drive (selected as Drive 0) has been referred to as the
master in industry terms and the second (selected as Drive 1) has been
referred to as the slave (see Figure 5-3).
The designation as Drive 0 or Drive 1 may be made in a number of ways:
- a switch on the drive
- a jumper plug on the drive
- use of the Cable Select (CSEL) pin
Data is transferred in parallel (8 or 16 bits) either to or from host memory
to the drive's buffer under the direction of commands previously transferred
from the host. The drive performs all of the operations necessary to properly
write data to, or read data from, the disk media. Data read from the media is
stored in the drive's buffer pending transfer to the host memory and data is
transferred from the host memory to the drive's buffer to be written to the
media.
+-----------------------------------------------------+
| |
| HOST |
| |
+---------------^-------------------------------------+
| ATA Interface
| _____________________
|/ |
+------v--+ +------v--+
| DRIVE 0 | | DRIVE 1 |
+---------+ +---------+
FIGURE 5-1: ATA INTERFACE TO EMBEDDED BUS PERIPHERALS
+-----------------------------------------------------+
| |
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