📄 ata-r32.txt
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Copies of this proposal may be purchased from: BSR X3.221
Global Engineering, 2805 McGaw St, Irvine, CA 92714 X3T9.2/90-143
800-854-7179 714-261-1455
working draft proposed American National
Standard for Information Systems -
ATA (AT Attachment)
Rev 3.2 October 16, 1992
Secretariat
Computer and Business Equipment Manufacturers Association (CBEMA)
Abstract: This standard defines an integrated bus interface between disk
drives and host processors. It provides a common point of attachment for
systems manufacturers, system integrators, and suppliers of intelligent
peripherals.
draft proposed American National Standard
This is a draft proposed American National Standard of Accredited Standards
Committee X3. As such this is not a completed standard. The X3T9 Technical
Committee may modify this document as a result of comments received during
public review and its approval as a standard.
POINTS OF CONTACT:
John B. Lohmeyer I. Dal Allan
Chairman X3T9.2 Vice-Chairman X3T9.2
NCR ENDL
1635 Aeroplaza Dr 14426 Black Walnut Court
Colorado Springs CO 80916 Saratoga CA 95070
719-596-5795 x362 408-867-6630
An electronic copy of this document is available from the SCSI Bulletin Board
(719-574-0424).
This document has been prepared according to the style guide of the ISO
(International Organization of Standards).
If this document was printed in a 2-up form directly from the printer, NOTEs
had to be adjusted to fit into a half-page, which may have resulted in an
imperfect representation of the format within the NOTE. This is most likely to
occur if a series of NOTEs are mixed in without any line separation.
ATA was forwarded in August 1991 from X3T9.2 to X3T9 for further processing as
an American National Standard. X3T9 authorized a letter ballot on forwarding
this document as a preliminary draft proposed American National Standard.
X3 authorized a Public Review of Rev 3.0 of the document as a draft proposed
American National Standard.
This revision reflects comments received during the 4-month Public Review, and
recommendations made by the ATA Working Group of X3T9.2. Amongst the technical
changes included herein that differ from the Rev 3.0 document are:
NOP:
Additional command
Multiword DMA:
Additional timing chart
Additions to Identify Drive
Additions to Set Features
SFF 44-pin:
Additional Annex
LBA (Logical Block Addressing):
Additional description
Additions to Identify Drive
Additions to Register descriptions
All changes from Rev 3.0 are marked in bold.
Foreword: This Foreword is not part of American National Standard X3.***-199x.
When the first IBM PC (Personal Computer) (tm) was introduced, there was no
hard disk capability for storage. Successive generations of product resulted
in the inclusion of a hard disk as the primary storage device. When the PC AT
(tm) was developed, a hard disk was the key to system performance, and the
controller interface became a de facto industry interface for the inclusion of
hard disks in PC ATs.
The price of desktop systems has declined rapidly because of the degree of
integration to reduce the number of components and interconnects required to
build a product. A natural outgrowth of this integration was the inclusion of
controller functionality into the hard disk.
In October 1988 a number of peripheral suppliers formed the Common Access
Method Committee to encourage an industry-wide effort to adopt a common
software interface to dispatch input/output requests to SCSI peripherals.
Although this was the primary objective, a secondary goal was to specify what
is known as the AT Attachment interface.
Suggestions for improvement of this standard will be welcome. They should be
sent to the Computer and Business Equipment Manufacturers Association, 311
First Street N.W., Suite 500, Washington, DC 20001.
This standard was processed and approved for submittal to ANSI by the
Accredited Standards Committee on Information Processing Systems, X3.
Committee approval of this standard does not necessarily imply that all
committee members voted for its approval. At the time it approved this
standard, the X3 Committee had the following members:
X3 Committee list goes here:
Subcommittee X3T9 on I/O interfaces, which reviewed this standard, had the
following members:
X3T9 Committee list goes here:
Task Group X3T9.2 on Lower-Level Interfaces, which completed the development
of this standard, had the following members:
X3T9.2 Committee list goes here:
The initial development work on this standard was done by the CAM Committee.
The membership of the CAM Committee consisted of the following organizations:
Adaptec Data Technology NCR
AMD Eastman Kodak Olivetti
Apple Emulex Quantum
AT&T Bell Labs Fujitsu uElectronics Scientific Micro Systems
Caliper Future Domain Seagate
Cambrian Systems Hewlett Packard Sony
Cipher Data IBM Storage Dimensions
Cirrus Logic Imprimis Sun Microsystems
Columbia Data Interactive Systems Syquest Technology
CompuAdd JVC Sytron
Conner Peripherals LMS OSD Trantor
Dell Computer Maxtor Western Digital
Digital Equipment Micropolis
DPT Miniscribe
TABLE OF CONTENTS
1. Scope 1
1.1 Description of Clauses 1
2. References 1
3. General Description 1
3.1 Structure 2
4. Definitions and Conventions 2
4.1 Definitions 2
4.2 Conventions 3
5. Interface Cabling Requirements 3
5.1 Configuration 3
5.2 Addressing Considerations 4
5.3 DC Cable and Connector 5
5.3.1 4-Pin Power 5
5.3.2 3-Pin Power 5
5.3.3 Device Grounding 6
5.4 I/O Connector 6
5.5 I/O Cable 6
6. Physical Interface 7
6.1 Signal Conventions 7
6.2 Signal Summary 7
6.3 Signal Descriptions 9
6.3.1 CS1FX- (Drive chip Select 0) 9
6.3.2 CS3FX- (Drive chip Select 1) 9
6.3.3 DA0-2 (Drive Address Bus) 10
6.3.4 DASP- (Drive Active/Drive 1 Present) 10
6.3.5 DD0-DD15 (Drive Data Bus) 10
6.3.6 DIOR- (Drive I/O Read) 10
6.3.7 DIOW- (Drive I/O Write) 10
6.3.8 DMACK- (DMA Acknowledge) (Optional) 10
6.3.9 DMARQ (DMA Request) (Optional) 11
6.3.10 INTRQ (Drive Interrupt) 11
6.3.11 IOCS16- (Drive 16-bit I/O) 11
6.3.12 IORDY (I/O Channel Ready) (Optional) 12
6.3.13 PDIAG- (Passed Diagnostics) 12
6.3.14 RESET- (Drive Reset) 12
6.3.15 SPSYNC:CSEL (Spindle Synchronization/Cable Select)
(Optional) 12
6.3.15.1 SPSYNC (Spindle Synchronization) (Optional) 13
6.3.15.2 CSEL (Cable Select) (Optional) 13
7. Logical Interface 14
7.1 General 14
7.1.1 Bit Conventions 14
7.1.2 Environment 14
7.2 I/O Register Descriptions 15
7.2.1 Alternate Status Register 16
7.2.2 Command Register 16
7.2.3 Cylinder High Register 16
7.2.4 Cylinder Low Register 17
7.2.5 Data Register 17
7.2.6 Device Control Register 17
7.2.7 Drive Address Register 17
7.2.8 Drive/Head Register 18
7.2.9 Error Register 18
7.2.10 Features Register 19
7.2.11 Sector Count Register 19
7.2.12 Sector Number Register 19
7.2.13 Status Register 19
8. Programming Requirements 21
8.1 Reset Response 21
8.2 Translate Mode 22
8.3 Power Conditions 22
8.4 Error Posting 22
9. Command Descriptions 23
9.1 Acknowledge Media Change (Removable) 25
9.2 Boot - Post-Boot (Removable) 25
9.3 Boot - Pre-Boot (Removable) 25
9.4 Check Power Mode 26
9.5 Door Lock (Removable) 26
9.6 Door Unlock (Removable) 26
9.7 Execute Drive Diagnostic 26
9.8 Format Track 27
9.9 Identify Drive 28
9.9.1 Word 1: Number of cylinders 29
9.9.2 Word 3: Number of heads 29
9.9.3 Word 4: Number of unformatted bytes per track 29
9.9.4 Word 5: Number of unformatted bytes per sector 30
9.9.5 Word 6: Number of sectors per track 30
9.9.6 Word 10-19: Serial Number 30
9.9.7 Word 20: Buffer Type 30
9.9.8 Word 22: ECC bytes Available on Read/Write Long Commands 30
9.9.9 Word 23-26: Firmware Revision 30
9.9.10 Word 27-46: Model Number 30
9.9.11 Word 51: PIO data transfer cycle timing mode 30
9.9.12 Word 52: DMA data transfer cycle timing mode 30
9.9.13 Word 54: Number of current cylinders 31
9.9.14 Word 55: Number of current heads 31
9.9.15 Word 56: Number of current sectors per track 31
9.9.16 Word 57-58: Current capacity in sectors 31
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