dm9000.c

开发板用的事博创的arm2410-s

#include <linux/init.h>    
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/dma.h>
#include <linux/spinlock.h>
#include <linux/crc32.h>
#include <linux/platform_device.h>
#include <linux/irq.h>

#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/regs-mem.h>
 
#define DM9KS_ID  0x90000A46
#define DM9010_ID  0x90100A46
#define DM9KS_NCR  0x00 /* Network control Reg.*/
#define DM9KS_NSR  0x01 /* Network Status Reg.*/
#define DM9KS_TCR  0x02 /* TX control Reg.*/
#define DM9KS_RXCR  0x05 /* RX control Reg.*/
#define DM9KS_BPTR  0x08
#define DM9KS_EPCR  0x0b
#define DM9KS_EPAR  0x0c
#define DM9KS_EPDRL  0x0d
#define DM9KS_EPDRH  0x0e
#define DM9KS_GPR  0x1f /* General purpose register */
#define DM9KS_TCR2  0x2d
#define DM9KS_SMCR  0x2f  /* Special Mode Control Reg.*/
#define DM9KS_ETXCSR  0x30 /* Early Transmit control/status Reg.*/
#define DM9KS_TCCR  0x31 /* Checksum cntrol Reg. */
#define DM9KS_RCSR  0x32 /* Receive Checksum status Reg.*/
#define DM9KS_MRCMDX  0xf0
#define DM9KS_MRCMD  0xf2
#define DM9KS_MDRAL  0xf4
#define DM9KS_MDRAH  0xf5
#define DM9KS_MWCMD  0xf8
#define DM9KS_TXPLL  0xfc
#define DM9KS_TXPLH  0xfd
#define DM9KS_ISR  0xfe
#define DM9KS_IMR  0xff
/*---------------------------------------------*/
#define DM9KS_REG05  0x30 /* SKIP_CRC/SKIP_LONG */ 
#define DM9KS_REGFF  0xA3 /* IMR */
#define DM9KS_DISINTR  0x80
#define DM9KS_PHY  0x40 /* PHY address 0x01 */
#define DM9KS_PKT_RDY  0x01 /* Packet ready to receive */
#define DM9KS_VID_L  0x28
#define DM9KS_VID_H  0x29
#define DM9KS_PID_L  0x2A
#define DM9KS_PID_H  0x2B
#define DM9KS_RX_INTR  0x01
#define DM9KS_TX_INTR  0x02
#define DM9KS_LINK_INTR  0x20
#define DM9KS_DWORD_MODE 1
#define DM9KS_BYTE_MODE  2
#define DM9KS_WORD_MODE  0
#define TRUE   1
#define FALSE   0
/* Number of continuous Rx packets */
#define CONT_RX_PKT_CNT 10 
#define DMFE_TIMER_WUT  jiffies+(HZ*5) /* timer wakeup time : 5 second */
#define CARDNAME "dm9ks"
#define MEM_MAPPED_IO 1
#ifdef MEM_MAPPED_IO
#define GETB(a)  *((volatile unsigned char *) (a))
#define GETW(a)  *((volatile unsigned short *) (a))
#define GETL(a)  *((volatile unsigned long *) (a))
#define PUTB(d,a) *((volatile unsigned char *) (a)) = d
#define PUTW(d,a) *((volatile unsigned short *) (a)) = d
#define PUTL(d,a) *((volatile unsigned long *) (a)) = d
#else
#define GETB(a)  inb(a)
#define GETW(a)  inw(a)
#define GETL(a)  inl(a)
#define PUTB(d,a) outb(d,a)
#define PUTW(d,a) outw(d,a)
#define PUTL(d,a) outl(d,a)
#endif
typedef struct _RX_DESC
{
        u8 rxbyte;
        u8 status;
        u16 length;
}RX_DESC;
typedef union{
        u8 buf[4];
        RX_DESC desc;
} rx_t;
enum DM9KS_PHY_mode {
        DM9KS_10MHD   = 0, 
        DM9KS_100MHD  = 1, 
        DM9KS_10MFD   = 4,
        DM9KS_100MFD  = 5, 
        DM9KS_AUTO    = 8, 
};
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
 
        u32 reset_counter;  /* counter: RESET */ 
        u32 reset_tx_timeout;  /* RESET caused by TX Timeout */ 
        u32 io_addr;   /* Register I/O base address */
        u32 io_data;   /* Data I/O address */
        int tx_pkt_cnt;
        u8 op_mode;   /* PHY operation mode */
        u8 io_mode;   /* 0:word, 2:byte */
        u8 device_wait_reset;  /* device state */
        u8 Speed;   /* current speed */
        int cont_rx_pkt_cnt;/* current number of continuos rx packets  */
        struct timer_list timer;
        struct net_device_stats stats;
        unsigned char srom[128];
        spinlock_t lock;
} board_info_t;
static struct net_device * dmfe_dev = NULL;
/* For module input parameter */
static int mode       = DM9KS_100MFD;
static int media_mode = DM9KS_100MFD;
/* function declaration ------------------------------------- */
static int dm9k_probe(struct net_device *, unsigned long);
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static void dmfe_tx_done(unsigned long);
static void dmfe_packet_receive(struct net_device *);
static int dmfe_stop(struct net_device *);
static struct net_device_stats * dmfe_get_stats(struct net_device *); 
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
static irqreturn_t dmfe_interrupt(int , void *);
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u8 ior(board_info_t *, int);
static void iow(board_info_t *, int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);
static void dm9000_hash_table(struct net_device *);
static void dmfe_timeout(struct net_device *);
static void dmfe_reset(struct net_device *);
/* DM9000 network baord routine ---------------------------- */
static int __init dm9k_probe(struct net_device *dev, unsigned long addr)
{
        struct board_info *db;    /* Point a board information structure */
        u32 id_val;
        u16 i, j;
        int retval;
          /* Search for DM9000 serial NIC */
        PUTB(DM9KS_VID_L, addr);
        id_val = GETB(addr + 2); /* Change offset to 2 ^^^^^ */
        PUTB(DM9KS_VID_H, addr);
        id_val |= GETB(addr + 2) << 8;
        PUTB(DM9KS_PID_L, addr);
        id_val |= GETB(addr + 2) << 16;
        PUTB(DM9KS_PID_H, addr);
        id_val |= GETB(addr + 2) << 24;
        if (id_val != DM9KS_ID && id_val != DM9010_ID) {
                /* Dm9k chip not found */
                printk("dmfe_probe(): DM9000 not found. ID=%08X\n", id_val);
                return -ENODEV;
                }
                
        printk("<DM9KS> I/O: %lx, VID: %x \n",addr, id_val);
        /* Allocated board information structure */
        memset(dev->priv, 0, sizeof(struct board_info));
        db = (board_info_t *)dev->priv;
        dmfe_dev    = dev;
        db->io_addr  = addr;
        db->io_data = addr + 2; /* Change offset to 2 ^^^^^ */
        /* driver system function */
                                
        dev->base_addr   = addr;
        dev->irq   = IRQ_EINT2;
        dev->open   = &dmfe_open;
        dev->hard_start_xmit  = &dmfe_start_xmit;
        dev->watchdog_timeo = HZ; 
        dev->tx_timeout  = dmfe_timeout;
        dev->stop   = &dmfe_stop;
        dev->get_stats   = &dmfe_get_stats;
        dev->set_multicast_list = &dm9000_hash_table;
        dev->do_ioctl   = &dmfe_do_ioctl;
        for(i=0,j=0x10; i<6; i++,j++)
          {
                db->srom[i] = ior(db, j);
               
          }
                        for (i = 0; i < 5; i++)
                                printk("%2.2x:", db->srom[i]);
       
        /* Set Node Address */
        for (i=0; i<6; i++)
                dev->dev_addr[i] = db->srom[i];
        retval = register_netdev(dev);
        if (retval == 0) {
                /* now, print out the card info, in a short format.. */
                printk("%s: at %#lx IRQ %d\n",
                        dev->name, dev->base_addr, dev->irq);
                if (dev->dma != (unsigned char)-1)
                        printk(" DMA %d\n", dev->dma);
                if (!is_valid_ether_addr(dev->dev_addr)) {
                        printk("%s: Invalid ethernet MAC address.  Please "
                               "set using ifconfig\n", dev->name);
                } else {
                        /* Print the Ethernet address */
                        printk("%s: Ethernet addr: ", dev->name);
                        for (i = 0; i < 5; i++)
                                printk("%2.2x:", dev->dev_addr[i]);
                        printk("%2.2x\n", dev->dev_addr[5]);
                }
        }
        return 0;
}

/*
  Open the interface.
  The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
        board_info_t *db = (board_info_t *)dev->priv;
        u8 reg_nsr;
        int i;
       
        if (request_irq(dev->irq,&dmfe_interrupt,0,dev->name,dev)) 
                return -EAGAIN;
        /* Grab the IRQ */
 set_irq_type(dev->irq, IRQT_RISING);
        /* Initilize DM910X board */
        dmfe_init_dm9000(dev);
 
        /* Init driver variable */
        db->reset_counter  = 0;
        db->reset_tx_timeout  = 0;
        db->cont_rx_pkt_cnt = 0;
        
        /* check link state and media speed */
        db->Speed =10;
        i=0;
        do {
                reg_nsr = ior(db,0x1);
                if(reg_nsr & 0x40) /* link OK!! */
                {
                        /* wait for detected Speed */
                        mdelay(200);
                        reg_nsr = ior(db,0x1);
                        if(reg_nsr & 0x80)
                                db->Speed =10;
                        else
                                db->Speed =100;
                        break;
                }
                i++;
                mdelay(1);
        }while(i<3000); /* wait 3 second  */
        //printk("i=%d  Speed=%d\n",i,db->Speed); 
        /* set and active a timer process */
        init_timer(&db->timer);
        db->timer.expires  = DMFE_TIMER_WUT * 2;
        db->timer.data   = (unsigned long)dev;
        db->timer.function  = &dmfe_timer;
        add_timer(&db->timer); //Move to DM9000 initiallization was finished.
         
        netif_start_queue(dev);
        return 0;
}
/* Set PHY operationg mode
*/
static void set_PHY_mode(board_info_t *db)
{
        u16 phy_reg0 = 0x1200;  /* Auto-negotiation & Restart Auto-negotiation */
        u16 phy_reg4 = 0x01e1;  /* Default flow control disable*/
        if ( !(db->op_mode & DM9KS_AUTO) ) // op_mode didn't auto sense */
        { 
                switch(db->op_mode) {
                        case DM9KS_10MHD:  phy_reg4 = 0x21; 
                                           phy_reg0 = 0x1000;
                                           break;
                        case DM9KS_10MFD:  phy_reg4 = 0x41; 
                                           phy_reg0 = 0x1100;
                                           break;
                        case DM9KS_100MHD: phy_reg4 = 0x81; 
                                           phy_reg0 = 0x3000;
                                               break;
                        case DM9KS_100MFD: phy_reg4 = 0x101; 
                                           phy_reg0 = 0x3100;
                                              break;
                        default: 
                                           break;
                } // end of switch
        } // end of if
        phy_write(db, 0, phy_reg0);
        phy_write(db, 4, phy_reg4);
}
/* 
        Initilize dm9000 board
*/
static void dmfe_init_dm9000(struct net_device *dev)
{
        board_info_t *db = (board_info_t *)dev->priv;
       
        /* set the internal PHY power-on, GPIOs normal, and wait 2ms */
        iow(db, DM9KS_GPR, 1);  /* Power-Down PHY */
        udelay(500);
        iow(db, DM9KS_GPR, 0); /* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
        udelay(20);  /* wait 2ms for PHY power-on ready */
        /* do a software reset and wait 20us */
        iow(db, DM9KS_NCR, 3);
        udelay(20);  /* wait 20us at least for software reset ok */
        iow(db, DM9KS_NCR, 3); /* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on */
        udelay(20);  /* wait 20us at least for software reset ok */
        /* I/O mode */
        db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
        /* Set PHY */