cfnand.h

wince5.0 bsp 下K9F2G08Flash的驱动源代码

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#ifndef __NAND_H__
#define __NAND_H__
//#define K9F1G08_SUPPORT	(1)
//20080130 the program can't run if using NAND_BLOCK_CNT .. definition
#define NAND_BLOCK_CNT          1024//(GetNumBlocks())      /* Each Plane has 1024 Blocks   */
#define NAND_PAGE_CNT           64//(GetSectorsPerBlock())            /* Each Block has 32 Pages      */
#define NAND_PAGE_SIZE          2048//(GetBytesPerSector())           /* Each Page has 512 Bytes      */
#define NAND_BLOCK_SIZE         (NAND_PAGE_CNT * NAND_PAGE_SIZE)
#define SECTOR_SIZE	                NAND_PAGE_SIZE//(GetBytesPerSector()) 
#define NUM_BLOCKS	NAND_BLOCK_CNT//(GetNumBlocks())
//20080130 by yqx

//  For flash chip that is bigger than 32 MB, we need to have 4 step address
//
//  Since we are using 64 MB NAND flash on SMDK2440, define NAND_SIZE_GT_32MB
//
#define NAND_SIZE_GT_32MB

#ifdef NAND_SIZE_GT_32MB
#define NEED_EXT_ADDR               1
#else
#define NEED_EXT_ADDR               0
#endif

//  Initialization value for configuration register
#define NFCONF_INIT                 0xF850
//#endif
#define CMD_READID              0x90        //  ReadID
#define CMD_READ                0x00        //  Read
#define CMD_READ1               0x30        //  Read1
#define CMD_READ2               0x30        //  Read2
#define CMD_RESET               0xff        //  Reset
#define CMD_ERASE               0x60        //  Erase phase 1
#define CMD_ERASE2              0xd0        //  Erase phase 2
#define CMD_WRITE               0x80        //  Write phase 1
#define CMD_WRITE2              0x10        //  Write phase 2
#define CMD_STATUS              0x70        //  Status read

//  Status bit pattern
#define STATUS_READY                0x40        //  Ready
#define STATUS_ERROR                0x01        //  Error

/* !!! Maximum Delay Setting, Please Adjust these value to Optimize */
//HCLK 133MHz
#define TACLS                   0     
#define TWRPH0                  6
#define TWRPH1                  2 
#define READ_REGISTER_ULONG(reg) \
    (*(volatile unsigned long * const)(reg))

#define WRITE_REGISTER_ULONG(reg, val) \
    (*(volatile unsigned long * const)(reg)) = (val)

#define READ_REGISTER_USHORT(reg) \
    (*(volatile unsigned short * const)(reg))

#define WRITE_REGISTER_USHORT(reg, val) \
    (*(volatile unsigned short * const)(reg)) = (val)

#define READ_REGISTER_UCHAR(reg) \
    (*(volatile unsigned char * const)(reg))

#define WRITE_REGISTER_UCHAR(reg, val) \
    (*(volatile unsigned char * const)(reg)) = (val)

#define NF_CMD(cmd)	            {s2440NAND->rNFCMMD   =  (cmd);}
#define NF_ADDR(addr)	        {s2440NAND->rNFADDR  =  (unsigned char)(addr);}	
#define NF_nFCE_L()	            {s2440NAND->rNFCONT &= ~(1 << 1);}
#define NF_nFCE_H()	            {s2440NAND->rNFCONT |=  (1 << 1);}
//#define NF_RSTECC()	            {s2440NAND->rNFCONT |=  (1 << 4);}
#define NF_RDDATA() 	        READ_REGISTER_UCHAR((PUCHAR)&s2440NAND->rNFDATA)
#define NF_WRDATA(data)         WRITE_REGISTER_UCHAR((PUCHAR)&s2440NAND->rNFDATA, data)
#define NF_DATA_R4()		READ_REGISTER_ULONG(&s2440NAND->rNFDATA)
#define NF_DATA_W4(val)		WRITE_REGISTER_ULONG(&s2440NAND->rNFDATA, (ULONG) (val))
#define NF_RDDATA16() 	        READ_REGISTER_USHORT((PUSHORT)&s2440NAND->rNFDATA)

#define NF_WAITRnB()              {while (!(s2440NAND->rNFSTAT & (1 << 0)));}       //added by yangrui 20080919
#define NF_WAITRB()             	{while (!(s2440NAND->rNFSTAT & (1 << 1)));} 

//#define NF_MECC_UnLock()	{s2440NAND->rNFCONT &= ~(1 << 5);}
//#define NF_MECC_Lock()		{s2440NAND->rNFCONT |=  (1 << 5);}
#define NF_CLEAR_RB()			{s2440NAND->rNFSTAT |=  (1 << 2);}
#define NF_DETECT_RB()		{while(!(s2440NAND->rNFSTAT & (1<<2)));}
//#define NF_ECC()					(s2440NAND->rNFMECC0)

//20080228 ADD ECC
#define NF_MECC_UnLock() {s2440NAND->rNFCONT &= ~(1<<5);}
#define NF_MECC_Lock() {s2440NAND->rNFCONT |= (1<<5);}
#define NF_RSTECC()	            {s2440NAND->rNFCONT |=  (1 << 4);}
#define NF_ECC()					(s2440NAND->rNFMECC0)
#define NF_MainError (s2440NAND->rNFESTAT0 & 0x3)
#define NF_MErrorDataNO ((s2440NAND->rNFESTAT0 >> 7) & 0x7FF)
#define NF_MErrorBitNO ((s2440NAND->rNFESTAT0 >> 4) & 0x7) 
//20080228 BY YQX
#endif    // __NAND_H_.