📄 gspi.h
字号:
/******************* (c) Marvell Semiconductor, Inc., 2001 ********************
*
* $HEADER&
*
* Purpose:
* This file contains MSU registers definition
*
* Notes:
*
*****************************************************************************/
#ifndef __GSPIREG_H_
#define __GSPIREG_H_
/*
===============================================================================
PUBLIC DEFINITIONS
===============================================================================
*/
/* GSPI Registers Offset. All the resgisters are at DWORD boundary */
#define DEVICEID_CTRL_REG 0x00
#define CHIPREV_REG 0x00
#define IO_READBASE_REG 0x04
#define IO_WRITEBASE_REG 0x08
#define IO_RDWRPORT_REG 0x0C
#define CMD_READBASE_REG 0x10
#define CMD_WRITEBASE_REG 0x14
#define CMD_RDWRPORT_REG 0x18
#define DATA_READBASE_REG 0x1C
#define DATA_WRITEBASE_REG 0x20
#define DATA_RDWRPORT_REG 0x24
#define SCRATCH_1_REG 0x28
#define SCRATCH_2_REG 0x2C
#define SCRATCH_3_REG 0x30
#define SCRATCH_4_REG 0x34
#define TX_FRAME_SEQ_NUM_REG 0x38
#define TX_FRAME_STATUS_REG 0x3C
#define HOST_INT_CTRL_REG 0x40
#define CARD_INT_CAUSE_REG 0x44
#define CARD_INT_STATUS_REG 0x48
#define CARD_INT_EVENT_MASK_REG 0x4C
#define CARD_INT_STATUS_MASK_REG 0x50
#define CARD_INT_RESET_SELECT_REG 0x54
#define HOST_INT_CAUSE_REG 0x58
#define HOST_INT_STATUS_REG 0x5C
#define HOST_INT_EVENT_MASK_REG 0x60
#define HOST_INT_STATUS_MASK_REG 0x64
#define HOST_INT_RESET_SELECT_REG 0x68
#define DELAY_READ_REG 0x6C
#define SPI_BUS_MODE_REG 0x70
#define BUS_MODE_16_NO_DELAY 0x02
#define BUS_MODE_16_CLK_DELAY 0x06
/* Bit definition for CARD_INT_CAUSE (Card Interrupt Cause) */
#define CIC_TxDnLdOvr B_BIT_0
#define CIC_RxUpLdOvr B_BIT_1
#define CIC_CmdDnLdOvr B_BIT_2
#define CIC_HostEvent B_BIT_3
#define CIC_CmdUpLdOvr B_BIT_4
#define CIC_PwrDown B_BIT_5
/* Bit definition for HOST_INT_EVENT_MASK_REG (Host Interrupt Event Mask) */
#define HIEM_TxDnLdRdy B_BIT_0
#define HIEM_RxUpLdRdy B_BIT_1
#define HIEM_CmdDnLdRdy B_BIT_2
#define HIEM_CardEvent B_BIT_3
#define HIEM_CmdUpLdRdy B_BIT_4
#define HIEM_IOWrFifoOvrflow B_BIT_5
#define HIEM_IORdFifoUndrflow B_BIT_6
#define HIEM_DATAWrFifoOvrflow B_BIT_7
#define HIEM_DATARdFifoUndrflow B_BIT_8
#define HIEM_CMDWrFifoOvrflow B_BIT_9
#define HIEM_CMDRdFifoUndrflow B_BIT_10
/* Bit definition for HOST_INT_STATUS_MASK_REG (Host Interrupt Status Mask) */
#define HISM_TxDnLdRdy B_BIT_0
#define HISM_RxUpLdRdy B_BIT_1
#define HISM_CmdDnLdRdy B_BIT_2
#define HISM_CardEvent B_BIT_3
#define HISM_CmdUpLdRdy B_BIT_4
#define HISM_IOWrFifoOvrflow B_BIT_5
#define HISM_IORdFifoUndrflow B_BIT_6
#define HISM_DATAWrFifoOvrflow B_BIT_7
#define HISM_DATARdFifoUndrflow B_BIT_8
#define HISM_CMDWrFifoOvrflow B_BIT_9
#define HISM_CMDRdFifoUndrflow B_BIT_10
/* Bit definition for HOST_INT_RESET_SELECT_REG (Host Interrupt Reset Select Mask) */
#define HIRS_TxDnLdRdy B_BIT_0
#define HIRS_RxUpLdRdy B_BIT_1
#define HIRS_CmdDnLdRdy B_BIT_2
#define HIRS_CardEvent B_BIT_3
#define HIRS_CmdUpLdRdy B_BIT_4
#define HIRS_IOWrFifoOvrflow B_BIT_5
#define HIRS_IORdFifoUndrflow B_BIT_6
#define HIRS_DATAWrFifoOvrflow B_BIT_7
#define HIRS_DATARdFifoUndrflow B_BIT_8
#define HIRS_CMDWrFifoOvrflow B_BIT_9
#define HIRS_CMDRdFifoUndrflow B_BIT_10
#define HIS_TxDnLdRdy B_BIT_0
#define HIS_RxUpLdRdy B_BIT_1
#define HIS_CmdDnLdRdy B_BIT_2
#define HIS_CardEvent B_BIT_3
#define HIS_CmdUpLdRdy B_BIT_4
#define HIS_WrFifoOvrflow B_BIT_5
#define HIS_RdFifoUndrflow B_BIT_6
#define HIS_WlanReady B_BIT_7
#define GSPI_BUS_DRR_DEF 5
#define GSPI_BUS_DRP_DEF 14
/* Bit definition for HOST_INT_CTRL_REG (Host interrupt control register) */
#define HIC_WakeUp B_BIT_0
/* Bit definition for SPU_BUS_MODE_REG (SPU Bus mode register)*/
#define SBM_DataFormat_2 B_BIT_2
/* The number of times to try when polling for status bits */
//#define MAX_FIRMWARE_POLL_TRIES 20
/* Value to check once the firmware is downloaded */
#define FIRMWARE_DNLD_OK 0x88888888
/* Value to write to indicate end of firmware dnld */
#define FIRMWARE_DNLD_END 0x0000
#define FIRMWARE_DNLD_PCKCNT 64
#define PKT_WAIT_TIME 100 // number of 10 us units
// code which will be in the scratch register after FW is initialized
#define GSPI_FW_INIT_CODE 0xFEDC
typedef LONG WLAN_API_STATUS;
//typedef LONG DWORD;
#define WLAN_API_STATUS_SUCCESS ((WLAN_API_STATUS)0x00000000L)
#define WLAN_API_STATUS_PENDING ((WLAN_API_STATUS)0x00000001L)
#define WLAN_API_STATUS_BUFFER_OVERFLOW ((WLAN_API_STATUS)0xC0000001L)
#define WLAN_API_STATUS_DEVICE_BUSY ((WLAN_API_STATUS)0xC0000002L)
#define WLAN_API_STATUS_UNSUCCESSFUL ((WLAN_API_STATUS)0xC0000003L)
#define WLAN_API_STATUS_NOT_IMPLEMENTED ((WLAN_API_STATUS)0xC0000004L)
#define WLAN_API_STATUS_ACCESS_VIOLATION ((WLAN_API_STATUS)0xC0000005L)
#define WLAN_API_STATUS_INVALID_HANDLE ((WLAN_API_STATUS)0xC0000006L)
#define WLAN_API_STATUS_INVALID_PARAMETER ((WLAN_API_STATUS)0xC0000007L)
#define WLAN_API_STATUS_NO_SUCH_DEVICE ((WLAN_API_STATUS)0xC0000008L)
#define WLAN_API_STATUS_INVALID_DEVICE_REQUEST ((WLAN_API_STATUS)0xC0000009L)
#define WLAN_API_STATUS_NO_MEMORY ((WLAN_API_STATUS)0xC000000AL)
#define WLAN_API_STATUS_BUS_DRIVER_NOT_READY ((WLAN_API_STATUS)0xC000000BL)
#define WLAN_API_STATUS_DATA_ERROR ((WLAN_API_STATUS)0xC000000CL)
#define WLAN_API_STATUS_CRC_ERROR ((WLAN_API_STATUS)0xC000000DL)
#define WLAN_API_STATUS_INSUFFICIENT_RESOURCES ((WLAN_API_STATUS)0xC000000EL)
#define WLAN_API_STATUS_DEVICE_NOT_CONNECTED ((WLAN_API_STATUS)0xC0000010L)
#define WLAN_API_STATUS_DEVICE_REMOVED ((WLAN_API_STATUS)0xC0000011L)
#define WLAN_API_STATUS_DEVICE_NOT_RESPONDING ((WLAN_API_STATUS)0xC0000012L)
#define WLAN_API_STATUS_CANCELED ((WLAN_API_STATUS)0xC0000013L)
#define WLAN_API_STATUS_RESPONSE_TIMEOUT ((WLAN_API_STATUS)0xC0000014L)
#define WLAN_API_STATUS_DATA_TIMEOUT ((WLAN_API_STATUS)0xC0000015L)
#define WLAN_API_STATUS_DEVICE_RESPONSE_ERROR ((WLAN_API_STATUS)0xC0000016L)
#define WLAN_API_STATUS_DEVICE_UNSUPPORTED ((WLAN_API_STATUS)0xC0000017L)
#define WLAN_API_STATUS_SHUT_DOWN ((WLAN_API_STATUS)0xC0000018L)
#define WLAN_API_SUCCESS(Status) ((WLAN_API_STATUS)(Status) == WLAN_API_STATUS_SUCCESS)
typedef enum _WLAN_FW_STATUS {
FW_STATUS_READ_FAILED,
FW_STATUS_INITIALIZED,
FW_STATUS_UNINITIALIZED,
FW_STATUS_DOWNLOADED
} WLAN_FW_STATUS;
typedef void (*ISR_CB)(void *);
int GspiBusInit(PVOID pHC);
int GspiCardInit();
int GspiBusDeinit(PVOID pHC);
//int gspi_read_host_int_status(UCHAR *data);
int gspi_reenable_host_interrupt(USHORT mask);
int gspi_poll_host_int_status(USHORT bits);
int gspi_read_reg(USHORT reg, USHORT *data);
int gspi_write_reg(USHORT reg, USHORT data);
int gspi_read_iomem(UCHAR *data, USHORT reg, USHORT size);
int gspi_write_iomem(UCHAR *data, USHORT reg, USHORT size);
inline int gspi_read_reg32(USHORT offset, UINT *data);
inline int gspi_write_reg32(USHORT offset, UINT data);
int gspi_set_read_delay(int reg,int io);
void GspiBusRaiseBusClock(void);
NDIS_STATUS GSPI_RaiseBusClock(PVOID);
int GSPI_WaitForHostIntStatus();
extern WLAN_FW_STATUS GSPI_IsFirmwareLoaded( IN PVOID pv );
WLAN_API_STATUS GSPI_ReadLengthScratchRegister( IN PVOID pv, PUSHORT pVal );
//JKU: void gspx_set_callback(PVOID pHC, ISR_CB cb, void *data);
void GspiBusEnableInterrupt();
void GSPI_TurnOffPwr(void);
void GSPI_TurnOnPwr(void);
void GSPI_TurnOffLED(void);
void GSPI_TurnOnLED(void);
#define GSPIDownloadPkt(Adapter, DownloadPkt) GSPI_DownloadBuf(Adapter, (PUCHAR)(DownloadPkt), (DownloadPkt)->Len, 1 )
//for new power save
#define GSPIDownloadPktPs(Adapter, downloadPkt) GSPIDownloadPkt_Ps(Adapter, downloadPkt)
#define GspiHandleDelayedDnld(Adapter) gspi_handle_delayedDnld(Adapter)
#define MrvDrvWlanIntTimerHandler WLAN_IntTimerHandler
#endif /* __GSPIREG_H_ */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -