gspi_bus_2440.h

murata wifi 模块源代码

#if defined(IF_GSPI) && ( defined(SC2442_SPI))

#ifndef     __GSPI_BUS_S3C2440_H
#define     __GSPI_BUS_S3C2440_H

#include "gspx_bus.h"


//WinCE IRQ calculation
#define SYSINTR_NOP         0				// no processing required 
#define SYSINTR_DEVICES     8				// first base
// SYSINTR_FIRMWARE is the base for any interrupts defined in the OAL
#define SYSINTR_FIRMWARE   (SYSINTR_DEVICES + 8)
#define SYSINTR_WLAN       (SYSINTR_FIRMWARE + 22)   // 0x26  //XSY: for GSPI bus
#define SYSINTR_DMA1       (SYSINTR_FIRMWARE + 21)   // 0x25   for GSPI bus

/********* GPIO bit definitions *************/

#define GPIO(n) (1 << n)

// GPIO pin definition
// XSY: we use
//      gpio4 :  SCSn signal
//		gpio8 :  wlan interrupt
//		gpio11:  RSTn signal
#define PIN_SCSn		GPIO(6)	  //4 7
#define PIN_WLANINT		GPIO(8)
#define PIN_RSTn		GPIO(11)   //11

// Hardware parameters structure.
typedef struct __GSPI_HW_INFO__
{
    // G-spi controller registers.
    SSPreg* volatile	pSPIRegs;

    // DMA controller registers.
    DMAreg* volatile	pDMARegs;

    /* Pointer to GPIO Registers */
    IOPreg* volatile 	pGPIORegs;
    
	//CLKCTRL register
    CLKreg*  volatile    pCLKRegs; 

	UCHAR 			*dmaTxBuf;
	UCHAR 			*dmaTxRxBuf;
	UCHAR 			*dmaRxBuf;
    DWORD           dmaPhyTxBuf;
    DWORD           dmaPhyTxRxBuf;
    DWORD           dmaPhyRxBuf;
}
GSPI_HW_INFO, *pGSPI_HW_INFO;

extern pGSPI_HW_INFO g_pHwInfo;

#define BSP_GSPI_DMA_TX_BUF_SIZE 	0x2000
#define BSP_GSPI_DMA_RX_BUF_SIZE 	0x2000
#define BSP_GSPI_DMA_TX_RX_BUF_SIZE 0x2000

// Generic Bus Funcs
int GspiBusAcquireIO();
void GspiBusReleaseIO();

#define PHY_TX_REG_BASE                     0x59000010
#define PHY_RX_REG_BASE                     0x59000014

//===================== Register Configuration Constants ======================

//----- Register definitions for DISRCn control register -----
//
// bits[30-0] = start address of source data to transfer


//----- Register definitions for DISRCCn control register -----
//
#define SOURCE_PERIPHERAL_BUS				0x00000002
#define FIXED_SOURCE_ADDRESS				0x00000001


//----- Register definitions for DIDSTn control register -----
//
// bits[30-0] = start address of destination for the transfer


//----- Register definitions for DIDSTCn control register -----
//
#define DESTINATION_PERIPHERAL_BUS			0x00000002
#define FIXED_DESTINATION_ADDRESS			0x00000001


//----- Register definitions for DCONn control register -----
//
#define HANDSHAKE_MODE						0x80000000
#define DREQ_DACK_SYNC						0x40000000
#define GENERATE_INTERRUPT					0x20000000
#define SELECT_BURST_TRANSFER				0x10000000
#define SELECT_WHOLE_SERVICE_MODE			0x08000000

// bits[26-24] = select DMA source for the respective channel:
//------------------------------------------------------------
#define XDREQ0_DMA0							0x00000000
#define UART0_DMA0							0x01000000
#define MMC_DMA0							0x02000000
#define TIMER_DMA0							0x03000000
#define USB_EP1_DMA0						0x04000000
#define I2SSDO_DMA0							0x05000000
#define AC97PCMIN_DMA0						0x06000000	// AC97 PCMIN


#define XDREQ1_DMA1							0x00000000
#define UART1_DMA1							0x01000000
#define I2SSDI_DMA1							0x02000000
#define SPI_DMA1							0x03000000
#define USB_EP2_DMA1						0x04000000
#define AC97PCMOUT_DMA1						0x05000000	// AC97 PCMOUT
#define MMC_DMA1							0x06000000

#define I2SSDO_DMA2							0x00000000
#define I2SSDI_DMA2							0x01000000
#define MMC_DMA2							0x02000000
#define TIMER_DMA2							0x03000000
#define USB_EP3_DMA2						0x04000000
#define AC97PCMIN_DMA2						0x05000000	// AC97 PCMIN
#define AC97MICIN_DMA2						0x06000000	// AC97 MICIN

#define UART2_DMA3							0x00000000
#define MMC_DMA3							0x01000000
#define SPI_DMA3							0x02000000
#define TIMER_DMA3							0x03000000
#define USB_EP4_DMA3						0x04000000
#define AC97MICIN_DMA3						0x05000000	// AC97 MICIN
#define AC97PCMOUT_DMA3						0x06000000	// AC97 PCMOUT
//------------------------------------------------------------

#define DMA_TRIGGERED_BY_HARDWARE			0x00800000
#define NO_DMA_AUTO_RELOAD					0x00400000

// bits[21-20] = select transfer word size
//------------------------------------------------------------
#define TRANSFER_BYTE						0x00000000				// 8  bits
#define TRANSFER_HALF_WORD					0x00100000				// 16 bits
#define TRANSFER_WORD						0x00200000				// 32 bits
//
// bits[19-0] = used to specify the number of transfer operations in a DMA request



//----- Register definitions for DSTATn status register -----
#define DMA_TRANSFER_IN_PROGRESS			0x00100000
//
// bits[19-0] = the current transfer count


//----- Register definitions for DCSRCn configuration register -----
//
// bits[30-0] = current source address for DMA channel n


//----- Register definitions for DCDSTn configuration register -----
//
// bits[30-0] = current destination address for DMA channel n


//----- Register definitions for DMASKTRIGn configuration register -----
#define STOP_DMA_TRANSFER					0x00000004
#define ENABLE_DMA_CHANNEL					0x00000002
#define DMA_SW_TRIGGER						0x00000001



//=============================================================================

#endif /* __GSPI_BUS_S3C2440_H */

#endif /* GSPI, 2440 */