clockgen_rtl.vhd

COriac Algorithm code

-- hds header_start
-- hds header_end
--  hds header_start
-- 
--  VHDL Entity Shared_lib.clockgen.symbol
-- 
--  Created:
--           by - Hans.UNKNOWN (ACHILLES)
--           at - 09:55:07 03/29/03
-- 
--  Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
-- 
--  This library is free software; you can redistribute it and/or modify it 
--  under the terms of the GNU Lesser General Public License as published 
--  by the Free Software Foundation; either version 2.1 of the License, or 
--  (at your option) any later version.
-- 
--  This library is distributed in the hope that it will be useful, but WITHOUT 
--  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
--  License for more details.    See http://www.gnu.org/copyleft/lesser.txt
-- 
--  hds header_end
-- 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY clockgen IS
   GENERIC( 
      PERIOD : time := 67.8168403 ns
   );
   PORT( 
      clk         : OUT    std_logic;
      async_reset : OUT    std_logic;
      sync_reset  : OUT    std_logic
   );

-- Declarations

END clockgen ;

-- hds interface_end


-- hds interface_end

ARCHITECTURE rtl OF clockgen IS
BEGIN

process      
    variable c:std_logic :='0';
	begin
      	c := not c;
      	clk <= c;  
      	wait for PERIOD/2;
    end process;	

process      
	begin
     	async_reset <= '1';	 -- assert async reset
		wait for PERIOD*6;
		wait for PERIOD+ 63 ns; -- (change to random number generator)
		async_reset <= '0';
		wait;
    end process;	

process      
	begin
     	sync_reset <= '1';	 -- assert synchronous reset
		wait for PERIOD*6;
		sync_reset <= '0';
		wait;
    end process;		

END rtl;