cordic_tb_struct.vhd

COriac Algorithm code

-- hds header_start
--
-- VHDL Entity Cordic.cordic_tb.symbol
--
-- Created:
--          by - Hans.UNKNOWN (ACHILLES)
--          at - 14:55:59 03/29/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- This library is free software; you can redistribute it and/or modify it 
-- under the terms of the GNU Lesser General Public License as published 
-- by the Free Software Foundation; either version 2.1 of the License, or 
-- (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful, but WITHOUT 
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
-- License for more details.	 See http://www.gnu.org/copyleft/lesser.txt
--
-- hds header_end


ENTITY cordic_tb IS
   GENERIC( 
      WIDTH       : integer := 24;
      COMPARE_END : Integer := 8
   );
-- Declarations

END cordic_tb ;

-- hds interface_end
--
-- VHDL Architecture Cordic.cordic_tb.struct
--
-- Created:
--          by - Hans.UNKNOWN (ACHILLES)
--          at - 14:55:59 03/29/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- This library is free software; you can redistribute it and/or modify it 
-- under the terms of the GNU Lesser General Public License as published 
-- by the Free Software Foundation; either version 2.1 of the License, or 
-- (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful, but WITHOUT 
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
-- License for more details.	 See http://www.gnu.org/copyleft/lesser.txt

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;

LIBRARY Cordic;
USE Cordic.cordic_pkg.ALL;
LIBRARY std;
USE std.textio.all;

LIBRARY Cordic;

ARCHITECTURE struct OF cordic_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL angle       : std_logic_vector(WIDTH-1 DOWNTO 0);
   SIGNAL async_reset : std_logic;
   SIGNAL clk         : std_logic;
   SIGNAL cos         : std_logic_vector(WIDTH-1 DOWNTO 0);
   SIGNAL done        : std_logic;
   SIGNAL reset       : std_logic;
   SIGNAL sin         : std_logic_vector(WIDTH-1 DOWNTO 0);
   SIGNAL start       : std_logic;


   -- Component Declarations
   COMPONENT clockgen
   GENERIC (
      PERIOD : time := 67.8168403 ns
   );
   PORT (
      clk         : OUT    std_logic ;
      async_reset : OUT    std_logic ;
      sync_reset  : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT cordic
   GENERIC (
      WIDTH : integer := 24
   );
   PORT (
      clk   : IN     std_logic ;
      reset : IN     std_logic ;                          -- Active low reset
      angle : IN     std_logic_vector (WIDTH-1 DOWNTO 0); -- input radian
      sin   : OUT    std_logic_vector (WIDTH-1 DOWNTO 0);
      cos   : OUT    std_logic_vector (WIDTH-1 DOWNTO 0);
      start : IN     std_logic ;
      done  : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT cordic_tester
   GENERIC (
      WIDTH       : integer := 24;
      COMPARE_END : integer := 8;
      FILENAME    : string  := "../src/cordic_tester/behavioral.vhd.info/testvec.txt"
   );
   PORT (
      clk   : IN     std_logic ;
      cos   : IN     std_logic_vector (WIDTH-1 DOWNTO 0);
      done  : IN     std_logic ;
      reset : IN     std_logic ;
      sin   : IN     std_logic_vector (WIDTH-1 DOWNTO 0);
      angle : OUT    std_logic_vector (WIDTH-1 DOWNTO 0);
      start : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clockgen USE ENTITY Cordic.clockgen;
   FOR ALL : cordic USE ENTITY Cordic.cordic;
   FOR ALL : cordic_tester USE ENTITY Cordic.cordic_tester;
   -- pragma synthesis_on


BEGIN

   -- ModuleWare code for instance 'I3' of 'inv'
      reset <= NOT(async_reset);
   -- Instance port mappings.
   I4 : clockgen
      GENERIC MAP (
         PERIOD => 67.8168403 ns
      )
      PORT MAP (
         clk         => clk,
         async_reset => async_reset,
         sync_reset  => OPEN
      );
   I0 : cordic
      GENERIC MAP (
         WIDTH => WIDTH
      )
      PORT MAP (
         clk   => clk,
         reset => reset,
         angle => angle,
         sin   => sin,
         cos   => cos,
         start => start,
         done  => done
      );
   I1 : cordic_tester
      GENERIC MAP (
         WIDTH       => WIDTH,
         COMPARE_END => COMPARE_END,
         FILENAME    => "../src/cordic_tester/behavioral.vhd.info/testvec.txt"
      )
      PORT MAP (
         clk   => clk,
         cos   => cos,
         done  => done,
         reset => reset,
         sin   => sin,
         angle => angle,
         start => start
      );

END struct;