fsm_synthesis.vhd

COriac Algorithm code

-- hds header_start
--
-- VHDL Entity Cordic.fsm.symbol
--
-- Created:
--          by - Hans.UNKNOWN (ACHILLES)
--          at - 14:55:58 03/29/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- This library is free software; you can redistribute it and/or modify it 
-- under the terms of the GNU Lesser General Public License as published 
-- by the Free Software Foundation; either version 2.1 of the License, or 
-- (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful, but WITHOUT 
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
-- License for more details.	 See http://www.gnu.org/copyleft/lesser.txt
--
-- hds header_end
-- ------------------------------------------------------------------------------
-- Version   Author          Date          Changes
-- 0.1       Hans Tiggeler   10/03/2000    Tested on Modelsim SE 5.5
-- ==============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY fsm IS
   PORT( 
      clk   : IN     std_logic;
      reset : IN     std_logic;                      -- Active low reset
      start : IN     std_logic;
      cnt   : IN     std_logic_vector (4 DOWNTO 0);
      init  : OUT    std_logic;
      load  : OUT    std_logic;
      done  : OUT    std_logic
   );

-- Declarations

END fsm ;

-- hds interface_end
--
-- VHDL Architecture Cordic.fsm.synthesis
--
-- Created:
--          by - Hans.UNKNOWN (ACHILLES)
--          at - 14:55:58 03/29/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- This library is free software; you can redistribute it and/or modify it 
-- under the terms of the GNU Lesser General Public License as published 
-- by the Free Software Foundation; either version 2.1 of the License, or 
-- (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful, but WITHOUT 
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
-- License for more details.	 See http://www.gnu.org/copyleft/lesser.txt



ARCHITECTURE synthesis OF fsm IS

   -- Architecture Declarations
   TYPE STATE_TYPE IS (
      s0,
      s1,
      s2
   );

   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF synthesis : ARCHITECTURE IS "state" ;


   -- Declare current and next state signals
   SIGNAL state : STATE_TYPE ;
   SIGNAL nextstate : STATE_TYPE ;

BEGIN

   ----------------------------------------------------------------------------
   clocked : PROCESS(
      clk,
      reset
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (reset='0') THEN
         state <= s0;
         -- Reset Values
      ELSIF (clk'EVENT AND clk = '1') THEN
         state <= nextstate;
         -- Default Assignment To Internals

      END IF;

   END PROCESS clocked;

   ----------------------------------------------------------------------------
   state_nextstate : PROCESS (
      cnt,
      start,
      state
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE state IS
      WHEN s0 =>
         IF (start='1') THEN
            nextstate <= s1;
         ELSE
            nextstate <= s0;
         END IF;
      WHEN s1 =>
         IF (cnt="11111") THEN
            nextstate <= s2;
         ELSE
            nextstate <= s1;
         END IF;
      WHEN s2 =>
         IF (start='0') THEN
            nextstate <= s0;
         ELSE
            nextstate <= s2;
         END IF;
      WHEN OTHERS =>
         nextstate <= s0;
      END CASE;

   END PROCESS state_nextstate;

   ----------------------------------------------------------------------------
   output : PROCESS (
      state
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      -- Default Assignment To Internals

      -- Combined Actions
      CASE state IS
      WHEN s0 =>
         done <= '0';
         init <= '1';
         load <= '0';
      WHEN s1 =>
         done <= '0';
         init <= '0';
         load <= '1';
      WHEN s2 =>
         done <= '1';
         init <= '0';
         load <= '0';
      WHEN OTHERS =>
         done <= '-';
         init <= '-';
         load <= '-';               
            
      END CASE;

   END PROCESS output;

   -- Concurrent Statements

END synthesis;