📄 interface
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DocumentHdrVersion "1.1"
Header (DocumentHdr
packageRefs [
(PackageRef
library "ieee"
unitName "std_logic_1164"
itemName "all"
)
(PackageRef
library "ieee"
unitName "std_logic_arith"
itemName "all"
)
(PackageRef
library "ieee"
unitName "std_logic_unsigned"
itemName "all"
)
(PackageRef
library "Cordic"
unitName "cordic_pkg"
itemName "all"
)
(PackageRef
library "std"
unitName "textio"
itemName "all"
)
]
)
version "15.1"
appVersion "2002.1b (Build 7)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\hdl"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src"
)
(vvPair
variable "appl"
value "HDL Designer - Pro"
)
(vvPair
variable "d"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester"
)
(vvPair
variable "d_logical"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester"
)
(vvPair
variable "date"
value "03/29/03"
)
(vvPair
variable "day"
value "Sat"
)
(vvPair
variable "day_long"
value "Saturday"
)
(vvPair
variable "dd"
value "29"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "ACHILLES"
)
(vvPair
variable "library"
value "Cordic"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\work_ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\work_ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\work_mti"
)
(vvPair
variable "mm"
value "03"
)
(vvPair
variable "month"
value "Mar"
)
(vvPair
variable "month_long"
value "March"
)
(vvPair
variable "p"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester\\interface"
)
(vvPair
variable "p_logical"
value "D:\\DEMO\\demo_hdl_designer\\Cordic\\src\\cordic_tester\\interface"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "time"
value "11:00:10"
)
(vvPair
variable "unit"
value "cordic_tester"
)
(vvPair
variable "user"
value "Hans"
)
(vvPair
variable "version"
value "2002.1b (Build 7)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
)
uid 86,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 892,0
ps "OnEdgeStrategy"
shape (Triangle
uid 893,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
n "angle"
t "std_logic_vector"
b "(WIDTH-1 downto 0)"
m 1
o 7
r 6
d 0
s 0
sf 1
tg (CPTG
uid 894,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 895,0
va (VaSet
)
xt "16000,7500,23800,8500"
st "angle : (WIDTH-1:0)"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 896,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,6400,84000,7200"
st "angle : OUT std_logic_vector (WIDTH-1 downto 0) ;
"
)
)
*3 (CptPort
uid 897,0
ps "OnEdgeStrategy"
shape (Triangle
uid 898,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
n "clk"
t "std_logic"
o 6
r 1
d 0
s 0
sf 1
tg (CPTG
uid 899,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 900,0
va (VaSet
)
xt "16000,9500,16900,10500"
st "clk"
blo "16000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 901,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,2400,71000,3200"
st "clk : IN std_logic ;
"
)
)
*4 (CptPort
uid 902,0
ps "OnEdgeStrategy"
shape (Triangle
uid 903,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,10625,37750,11375"
)
n "cos"
t "std_logic_vector"
b "(WIDTH-1 downto 0)"
o 7
r 2
d 0
s 0
sf 1
tg (CPTG
uid 904,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 905,0
va (VaSet
)
xt "28900,10500,36000,11500"
st "cos : (WIDTH-1:0)"
ju 2
blo "36000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 906,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,3200,84000,4000"
st "cos : IN std_logic_vector (WIDTH-1 downto 0) ;
"
)
)
*5 (CptPort
uid 907,0
ps "OnEdgeStrategy"
shape (Triangle
uid 908,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27625,5250,28375,6000"
)
n "done"
t "std_logic"
o 6
r 3
d 0
s 0
sf 1
tg (CPTG
uid 909,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 910,0
ro 270
va (VaSet
)
xt "27500,7000,28500,8600"
st "done"
ju 2
blo "28300,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 911,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,4000,71000,4800"
st "done : IN std_logic ;
"
)
)
*6 (CptPort
uid 912,0
ps "OnEdgeStrategy"
shape (Triangle
uid 913,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
n "reset"
t "std_logic"
o 7
r 4
d 0
s 0
sf 1
tg (CPTG
uid 914,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 915,0
va (VaSet
)
xt "16000,11500,17700,12500"
st "reset"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 916,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,4800,71000,5600"
st "reset : IN std_logic ;
"
)
)
*7 (CptPort
uid 917,0
ps "OnEdgeStrategy"
shape (Triangle
uid 918,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,7625,37750,8375"
)
n "sin"
t "std_logic_vector"
b "(WIDTH-1 downto 0)"
o 6
r 5
d 0
s 0
sf 1
tg (CPTG
uid 919,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 920,0
va (VaSet
)
xt "29100,7500,36000,8500"
st "sin : (WIDTH-1:0)"
ju 2
blo "36000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 921,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,5600,84000,6400"
st "sin : IN std_logic_vector (WIDTH-1 downto 0) ;
"
)
)
*8 (CptPort
uid 922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 923,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "22625,5250,23375,6000"
)
n "start"
t "std_logic"
m 1
o 7
r 7
d 0
s 0
sf 1
tg (CPTG
uid 924,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 925,0
ro 270
va (VaSet
)
xt "22500,7000,23500,8500"
st "start"
ju 2
blo "23300,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 926,0
va (VaSet
font "Courier New,8,0"
)
xt "56000,7200,70000,8000"
st "start : OUT std_logic
"
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,37000,13000"
)
oxt "15000,6000,37000,23000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,12,1"
)
xt "21450,8000,25150,9500"
st "Cordic"
blo "21450,9200"
)
second (Text
uid 12,0
va (VaSet
font "Arial,12,1"
)
xt "21450,9500,30550,11000"
st "cordic_tester"
blo "21450,10700"
)
)
gi *9 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,10,0"
)
xt "3000,4500,50400,10500"
st "Generic Declarations
WIDTH integer 24
COMPARE_END integer 8
FILENAME string \"../src/cordic_tester/behavioral.vhd.info/testvec.txt\"
"
)
header "Generic Declarations"
)
elements [
(GiElement
name "WIDTH"
type "integer"
value "24"
)
(GiElement
name "COMPARE_END"
type "integer"
value "8"
)
(GiElement
name "FILENAME"
type "string"
value "\"../src/cordic_tester/behavioral.vhd.info/testvec.txt\""
)
]
)
portInstanceVisAsIs 1
)
*10 (Grouping
uid 16,0
optionalChildren [
*11 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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