emif.c

TI DSPTI DSPTI DSPTI DSPTI DSP

#include <csl.h>
#include <csl_emif.h>
#include <csl_emifa.h>
#include <csl_emifb.h>
#include "emif.h"


void emif_init()
{

    /* EMIFB settings for 600/100 MHz operation */
    EMIFB_Config emifbCfg0v1 = {
        EMIFB_FMKS(GBLCTL, EK2RATE, FULLCLK)    |
        EMIFB_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFB_FMKS(GBLCTL, EK2EN, DISABLE)      |
        EMIFB_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFB_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFB_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFB_FMKS(GBLCTL, EK1EN, ENABLE),

        EMIFB_FMKS(CECTL, WRSETUP, OF(10))      |
        EMIFB_FMKS(CECTL, WRSTRB, OF(8))       |
        EMIFB_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFB_FMKS(CECTL, RDSETUP, OF(0))      |
        EMIFB_FMKS(CECTL, TA, OF(2))           |
        EMIFB_FMKS(CECTL, RDSTRB, OF(8))       |
        EMIFB_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFB_FMKS(CECTL, RDHLD, OF(0)),

        EMIFB_FMKS(CECTL, WRSETUP, OF(0))      |
        EMIFB_FMKS(CECTL, WRSTRB, OF(8))       |
        EMIFB_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFB_FMKS(CECTL, RDSETUP, OF(0))      |
        EMIFB_FMKS(CECTL, TA, OF(2))           |
        EMIFB_FMKS(CECTL, RDSTRB, OF(8))       |
        EMIFB_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFB_FMKS(CECTL, RDHLD, OF(0)),

        EMIFB_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFB_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFB_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFB_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFB_FMKS(CECTL, TA, DEFAULT)         |
        EMIFB_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFB_FMKS(CECTL, MTYPE, ASYNC8)      |
        EMIFB_FMKS(CECTL, RDHLD, DEFAULT),

        EMIFB_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFB_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFB_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFB_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFB_FMKS(CECTL, TA, DEFAULT)         |
        EMIFB_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFB_FMKS(CECTL, MTYPE, ASYNC8)      |
        EMIFB_FMKS(CECTL, RDHLD, DEFAULT),

        EMIFB_FMKS(SDCTL, SDBSZ, DEFAULT)      |
        EMIFB_FMKS(SDCTL, SDRSZ, DEFAULT)      |
        EMIFB_FMKS(SDCTL, SDCSZ, DEFAULT)      |
        EMIFB_FMKS(SDCTL, RFEN, DEFAULT)       |
        EMIFB_FMKS(SDCTL, INIT, DEFAULT)       |
        EMIFB_FMKS(SDCTL, TRCD, DEFAULT)       |
        EMIFB_FMKS(SDCTL, TRP, DEFAULT)        |
        EMIFB_FMKS(SDCTL, TRC, DEFAULT),

        EMIFB_FMKS(SDTIM, XRFR, DEFAULT)       |
        EMIFB_FMKS(SDTIM, PERIOD, DEFAULT),

        EMIFB_FMKS(SDEXT, WR2RD, DEFAULT)      |
        EMIFB_FMKS(SDEXT, WR2DEAC, DEFAULT)    |
        EMIFB_FMKS(SDEXT, WR2WR, DEFAULT)      |
        EMIFB_FMKS(SDEXT, R2WDQM, DEFAULT)     |
        EMIFB_FMKS(SDEXT, RD2WR, DEFAULT)      |
        EMIFB_FMKS(SDEXT, RD2DEAC, DEFAULT)    |
        EMIFB_FMKS(SDEXT, RD2RD, DEFAULT)      |
        EMIFB_FMKS(SDEXT, THZP, DEFAULT)       |
        EMIFB_FMKS(SDEXT, TWR, DEFAULT)        |
        EMIFB_FMKS(SDEXT, TRRD, DEFAULT)       |
        EMIFB_FMKS(SDEXT, TRAS, DEFAULT)       |
        EMIFB_FMKS(SDEXT, TCL, DEFAULT),

        EMIFB_CESEC_DEFAULT,
        EMIFB_CESEC_DEFAULT,
        EMIFB_CESEC_DEFAULT,
        EMIFB_CESEC_DEFAULT
    };

    /* EMIFA settings for 720/120 MHz operation */
      EMIFA_Config emifaCfg0v1 = {
        EMIFA_FMKS(GBLCTL, EK2RATE, FULLCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, DISABLE),

        EMIFA_FMKS(CECTL, WRSETUP, OF(10))     |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(10))     |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(10))     |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(10))     |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 11ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),

        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(1560)),

        EMIFA_FMKS(SDEXT, WR2RD, OF(0))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(2))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(1))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(0))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(1))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(0))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(1))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(4))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),

        EMIFA_CESEC_DEFAULT,
        EMIFA_CESEC_DEFAULT,
        EMIFA_CESEC_DEFAULT,
        EMIFA_CESEC_DEFAULT
    };



    /* Configure EMIFB for failsafe operation at 120MHz */
    EMIFA_config(&emifaCfg0v1);

  
}