xianshi.map.qmsg

这是一个给予FPGA的动态显示代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Web Edition " "Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 09 17:08:59 2009 " "Info: Processing started: Thu Apr 09 17:08:59 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off xianshi -c xianshi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xianshi -c xianshi" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xianshi.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file xianshi.v" { { "Info" "ISGN_ENTITY_NAME" "1 xianshi " "Info: Found entity 1: xianshi" {  } { { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led_latcha.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led_latcha.v" { { "Info" "ISGN_ENTITY_NAME" "1 led_latcha " "Info: Found entity 1: led_latcha" {  } { { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dc.v" { { "Info" "ISGN_ENTITY_NAME" "1 dc " "Info: Found entity 1: dc" {  } { { "dc.v" "" { Text "D:/动态显示/dc.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "drive.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file drive.v" { { "Info" "ISGN_ENTITY_NAME" "1 drive " "Info: Found entity 1: drive" {  } { { "drive.v" "" { Text "D:/动态显示/drive.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tim.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file tim.v" { { "Info" "ISGN_ENTITY_NAME" "1 tim " "Info: Found entity 1: tim" {  } { { "tim.v" "" { Text "D:/动态显示/tim.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "xianshi.v(8) " "Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(8): instance has no name" {  } { { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 8 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "drive.v(7) " "Critical Warning (10846): Verilog HDL Instantiation warning at drive.v(7): instance has no name" {  } { { "drive.v" "" { Text "D:/动态显示/drive.v" 7 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "xianshi.v(9) " "Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(9): instance has no name" {  } { { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 9 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "xianshi.v(10) " "Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(10): instance has no name" {  } { { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 10 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "xianshi " "Info: Elaborating entity \"xianshi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tim tim:comb_4 " "Info: Elaborating entity \"tim\" for hierarchy \"tim:comb_4\"" {  } { { "xianshi.v" "comb_4" { Text "D:/动态显示/xianshi.v" 8 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "drive drive:comb_5 " "Info: Elaborating entity \"drive\" for hierarchy \"drive:comb_5\"" {  } { { "xianshi.v" "comb_5" { Text "D:/动态显示/xianshi.v" 9 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dc drive:comb_5\|dc:comb_4 " "Info: Elaborating entity \"dc\" for hierarchy \"drive:comb_5\|dc:comb_4\"" {  } { { "drive.v" "comb_4" { Text "D:/动态显示/drive.v" 7 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_latcha led_latcha:comb_6 " "Info: Elaborating entity \"led_latcha\" for hierarchy \"led_latcha:comb_6\"" {  } { { "xianshi.v" "comb_6" { Text "D:/动态显示/xianshi.v" 10 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "tim:comb_4\|a\[0\]~0 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: \"tim:comb_4\|a\[0\]~0\"" {  } { { "tim.v" "a\[0\]~0" { Text "D:/动态显示/tim.v" 15 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 247 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "tim:comb_4\|lpm_counter:a_rtl_0 " "Info: Elaborated megafunction instantiation \"tim:comb_4\|lpm_counter:a_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 268 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "tim:comb_4\|lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter tim:comb_4\|lpm_counter:a_rtl_0 " "Info: Elaborated megafunction instantiation \"tim:comb_4\|lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"tim:comb_4\|lpm_counter:a_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf" 424 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tim:comb_4\|lpm_counter:a_rtl_0 " "Info: Instantiated megafunction \"tim:comb_4\|lpm_counter:a_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 9 " "Info: Parameter \"LPM_WIDTH\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "173 " "Info: Implemented 173 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "25 " "Info: Implemented 25 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "49 " "Info: Implemented 49 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "99 " "Info: Implemented 99 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 17:09:01 2009 " "Info: Processing ended: Thu Apr 09 17:09:01 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}