xianshi.tan.qmsg

这是一个给予FPGA的动态显示代码

{ "Info" "ITDB_FULL_TCO_RESULT" "sclk grn_data\[0\] led_latcha:comb_6\|grn_data\[0\] 15.300 ns register " "Info: tco from clock \"sclk\" to destination pin \"grn_data\[0\]\" through register \"led_latcha:comb_6\|grn_data\[0\]\" is 15.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns sclk 1 CLK PIN_79 74 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 74; CLK Node = 'sclk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns led_latcha:comb_6\|grn_data\[0\] 2 REG LC4_B2 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'led_latcha:comb_6\|grn_data\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { sclk led_latcha:comb_6|grn_data[0] } "NODE_NAME" } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk led_latcha:comb_6|grn_data[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out led_latcha:comb_6|grn_data[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.900 ns + Longest register pin " "Info: + Longest register to pin delay is 8.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_latcha:comb_6\|grn_data\[0\] 1 REG LC4_B2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'led_latcha:comb_6\|grn_data\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { led_latcha:comb_6|grn_data[0] } "NODE_NAME" } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(5.100 ns) 8.900 ns grn_data\[0\] 2 PIN PIN_38 0 " "Info: 2: + IC(3.800 ns) + CELL(5.100 ns) = 8.900 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'grn_data\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { led_latcha:comb_6|grn_data[0] grn_data[0] } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 57.30 % ) " "Info: Total cell delay = 5.100 ns ( 57.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 42.70 % ) " "Info: Total interconnect delay = 3.800 ns ( 42.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { led_latcha:comb_6|grn_data[0] grn_data[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { led_latcha:comb_6|grn_data[0] grn_data[0] } { 0.000ns 3.800ns } { 0.000ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk led_latcha:comb_6|grn_data[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out led_latcha:comb_6|grn_data[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { led_latcha:comb_6|grn_data[0] grn_data[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { led_latcha:comb_6|grn_data[0] grn_data[0] } { 0.000ns 3.800ns } { 0.000ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "drive:comb_5\|com_drv\[1\] work sclk 1.300 ns register " "Info: th for register \"drive:comb_5\|com_drv\[1\]\" (data pin = \"work\", clock pin = \"sclk\") is 1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns sclk 1 CLK PIN_79 74 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 74; CLK Node = 'sclk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns drive:comb_5\|com_drv\[1\] 2 REG LC5_C17 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_C17; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { sclk drive:comb_5|com_drv[1] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns work 1 PIN PIN_182 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_182; Fanout = 16; PIN Node = 'work'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { work } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 5.600 ns drive:comb_5\|com_drv\[1\] 2 REG LC5_C17 2 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC5_C17; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { work drive:comb_5|com_drv[1] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 71.43 % ) " "Info: Total cell delay = 4.000 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 28.57 % ) " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { work drive:comb_5|com_drv[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { work work~out drive:comb_5|com_drv[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { work drive:comb_5|com_drv[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { work work~out drive:comb_5|com_drv[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 17:09:12 2009 " "Info: Processing ended: Thu Apr 09 17:09:12 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}