xianshi.tan.qmsg

这是一个给予FPGA的动态显示代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sclk " "Info: Assuming node \"sclk\" is an undefined clock" {  } { { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sclk register drive:comb_5\|dc:comb_4\|a register drive:comb_5\|com_drv\[4\] 57.47 MHz 17.4 ns Internal " "Info: Clock \"sclk\" has Internal fmax of 57.47 MHz between source register \"drive:comb_5\|dc:comb_4\|a\" and destination register \"drive:comb_5\|com_drv\[4\]\" (period= 17.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.800 ns + Longest register register " "Info: + Longest register to register delay is 13.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns drive:comb_5\|dc:comb_4\|a 1 REG LC3_B15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B15; Fanout = 4; REG Node = 'drive:comb_5\|dc:comb_4\|a'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { drive:comb_5|dc:comb_4|a } "NODE_NAME" } } { "dc.v" "" { Text "D:/动态显示/dc.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns led_latcha:comb_6\|red_data\[0\]~33 2 COMB LC1_B15 19 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_B15; Fanout = 19; COMB Node = 'led_latcha:comb_6\|red_data\[0\]~33'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { drive:comb_5|dc:comb_4|a led_latcha:comb_6|red_data[0]~33 } "NODE_NAME" } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 7.500 ns drive:comb_5\|com_drv~1962 3 COMB LC3_B16 4 " "Info: 3: + IC(2.300 ns) + CELL(2.300 ns) = 7.500 ns; Loc. = LC3_B16; Fanout = 4; COMB Node = 'drive:comb_5\|com_drv~1962'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 9.900 ns drive:comb_5\|com_drv~1973 4 COMB LC2_B16 1 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 9.900 ns; Loc. = LC2_B16; Fanout = 1; COMB Node = 'drive:comb_5\|com_drv~1973'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 13.800 ns drive:comb_5\|com_drv\[4\] 5 REG LC8_B13 2 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 13.800 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns ( 58.70 % ) " "Info: Total cell delay = 8.100 ns ( 58.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 41.30 % ) " "Info: Total interconnect delay = 5.700 ns ( 41.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.800 ns" { drive:comb_5|dc:comb_4|a led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.800 ns" { drive:comb_5|dc:comb_4|a led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } { 0.000ns 0.600ns 2.300ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 1.800ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"sclk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns sclk 1 CLK PIN_79 74 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 74; CLK Node = 'sclk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns drive:comb_5\|com_drv\[4\] 2 REG LC8_B13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns sclk 1 CLK PIN_79 74 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 74; CLK Node = 'sclk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns drive:comb_5\|dc:comb_4\|a 2 REG LC3_B15 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_B15; Fanout = 4; REG Node = 'drive:comb_5\|dc:comb_4\|a'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { sclk drive:comb_5|dc:comb_4|a } "NODE_NAME" } } { "dc.v" "" { Text "D:/动态显示/dc.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|dc:comb_4|a } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|dc:comb_4|a } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|dc:comb_4|a } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|dc:comb_4|a } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "dc.v" "" { Text "D:/动态显示/dc.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.800 ns" { drive:comb_5|dc:comb_4|a led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.800 ns" { drive:comb_5|dc:comb_4|a led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } { 0.000ns 0.600ns 2.300ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 1.800ns 1.700ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|dc:comb_4|a } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|dc:comb_4|a } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "drive:comb_5\|com_drv\[4\] re sclk 18.000 ns register " "Info: tsu for register \"drive:comb_5\|com_drv\[4\]\" (data pin = \"re\", clock pin = \"sclk\") is 18.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.800 ns + Longest pin register " "Info: + Longest pin to register delay is 20.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns re 1 PIN PIN_58 4 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_58; Fanout = 4; PIN Node = 're'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { re } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(2.300 ns) 9.900 ns led_latcha:comb_6\|red_data\[0\]~33 2 COMB LC1_B15 19 " "Info: 2: + IC(4.100 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC1_B15; Fanout = 19; COMB Node = 'led_latcha:comb_6\|red_data\[0\]~33'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.400 ns" { re led_latcha:comb_6|red_data[0]~33 } "NODE_NAME" } } { "led_latcha.v" "" { Text "D:/动态显示/led_latcha.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 14.500 ns drive:comb_5\|com_drv~1962 3 COMB LC3_B16 4 " "Info: 3: + IC(2.300 ns) + CELL(2.300 ns) = 14.500 ns; Loc. = LC3_B16; Fanout = 4; COMB Node = 'drive:comb_5\|com_drv~1962'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 16.900 ns drive:comb_5\|com_drv~1973 4 COMB LC2_B16 1 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 16.900 ns; Loc. = LC2_B16; Fanout = 1; COMB Node = 'drive:comb_5\|com_drv~1973'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 20.800 ns drive:comb_5\|com_drv\[4\] 5 REG LC8_B13 2 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 20.800 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 55.77 % ) " "Info: Total cell delay = 11.600 ns ( 55.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.200 ns ( 44.23 % ) " "Info: Total interconnect delay = 9.200 ns ( 44.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "20.800 ns" { re led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "20.800 ns" { re re~out led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 4.100ns 2.300ns 0.600ns 2.200ns } { 0.000ns 3.500ns 2.300ns 2.300ns 1.800ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns sclk 1 CLK PIN_79 74 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 74; CLK Node = 'sclk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "xianshi.v" "" { Text "D:/动态显示/xianshi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns drive:comb_5\|com_drv\[4\] 2 REG LC8_B13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'drive:comb_5\|com_drv\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "drive.v" "" { Text "D:/动态显示/drive.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "20.800 ns" { re led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "20.800 ns" { re re~out led_latcha:comb_6|red_data[0]~33 drive:comb_5|com_drv~1962 drive:comb_5|com_drv~1973 drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 4.100ns 2.300ns 0.600ns 2.200ns } { 0.000ns 3.500ns 2.300ns 2.300ns 1.800ns 1.700ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { sclk drive:comb_5|com_drv[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { sclk sclk~out drive:comb_5|com_drv[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}