xianshi.hier_info

这是一个给予FPGA的动态显示代码

|xianshi
sclk => sclk~0.IN3
xrst => xrst~0.IN3
work => work~0.IN1
re => re~0.IN1
r_add[0] => r_add[0]~4.IN1
r_add[1] => r_add[1]~3.IN1
r_add[2] => r_add[2]~2.IN1
r_add[3] => r_add[3]~1.IN1
r_add[4] => r_add[4]~0.IN1
r_data[0] => r_data[0]~15.IN1
r_data[1] => r_data[1]~14.IN1
r_data[2] => r_data[2]~13.IN1
r_data[3] => r_data[3]~12.IN1
r_data[4] => r_data[4]~11.IN1
r_data[5] => r_data[5]~10.IN1
r_data[6] => r_data[6]~9.IN1
r_data[7] => r_data[7]~8.IN1
r_data[8] => r_data[8]~7.IN1
r_data[9] => r_data[9]~6.IN1
r_data[10] => r_data[10]~5.IN1
r_data[11] => r_data[11]~4.IN1
r_data[12] => r_data[12]~3.IN1
r_data[13] => r_data[13]~2.IN1
r_data[14] => r_data[14]~1.IN1
r_data[15] => r_data[15]~0.IN1
red_data[0] <= led_latcha:comb_6.port5
red_data[1] <= led_latcha:comb_6.port5
red_data[2] <= led_latcha:comb_6.port5
red_data[3] <= led_latcha:comb_6.port5
red_data[4] <= led_latcha:comb_6.port5
red_data[5] <= led_latcha:comb_6.port5
red_data[6] <= led_latcha:comb_6.port5
red_data[7] <= led_latcha:comb_6.port5
red_data[8] <= led_latcha:comb_6.port5
red_data[9] <= led_latcha:comb_6.port5
red_data[10] <= led_latcha:comb_6.port5
red_data[11] <= led_latcha:comb_6.port5
red_data[12] <= led_latcha:comb_6.port5
red_data[13] <= led_latcha:comb_6.port5
red_data[14] <= led_latcha:comb_6.port5
red_data[15] <= led_latcha:comb_6.port5
grn_data[0] <= led_latcha:comb_6.port6
grn_data[1] <= led_latcha:comb_6.port6
grn_data[2] <= led_latcha:comb_6.port6
grn_data[3] <= led_latcha:comb_6.port6
grn_data[4] <= led_latcha:comb_6.port6
grn_data[5] <= led_latcha:comb_6.port6
grn_data[6] <= led_latcha:comb_6.port6
grn_data[7] <= led_latcha:comb_6.port6
grn_data[8] <= led_latcha:comb_6.port6
grn_data[9] <= led_latcha:comb_6.port6
grn_data[10] <= led_latcha:comb_6.port6
grn_data[11] <= led_latcha:comb_6.port6
grn_data[12] <= led_latcha:comb_6.port6
grn_data[13] <= led_latcha:comb_6.port6
grn_data[14] <= led_latcha:comb_6.port6
grn_data[15] <= led_latcha:comb_6.port6
com_drv[0] <= drive:comb_5.port8
com_drv[1] <= drive:comb_5.port8
com_drv[2] <= drive:comb_5.port8
com_drv[3] <= drive:comb_5.port8
com_drv[4] <= drive:comb_5.port8
com_drv[5] <= drive:comb_5.port8
com_drv[6] <= drive:comb_5.port8
com_drv[7] <= drive:comb_5.port8
com_drv[8] <= drive:comb_5.port8
com_drv[9] <= drive:comb_5.port8
com_drv[10] <= drive:comb_5.port8
com_drv[11] <= drive:comb_5.port8
com_drv[12] <= drive:comb_5.port8
com_drv[13] <= drive:comb_5.port8
com_drv[14] <= drive:comb_5.port8
com_drv[15] <= drive:comb_5.port8
led_clk <= led_clk~0.DB_MAX_OUTPUT_PORT_TYPE


|xianshi|tim:comb_4
sclk => a[7].CLK
sclk => a[6].CLK
sclk => a[5].CLK
sclk => a[4].CLK
sclk => a[3].CLK
sclk => a[2].CLK
sclk => a[1].CLK
sclk => a[0].CLK
sclk => led_clk~reg0.CLK
sclk => a[8].CLK
xrst => a[7].ACLR
xrst => a[6].ACLR
xrst => a[5].ACLR
xrst => a[4].ACLR
xrst => a[3].ACLR
xrst => a[2].ACLR
xrst => a[1].ACLR
xrst => a[0].ACLR
xrst => a[8].ACLR
led_clk <= led_clk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|xianshi|drive:comb_5
sclk => sclk~0.IN1
xrst => com_drv[14]~reg0.ACLR
xrst => com_drv[13]~reg0.ACLR
xrst => com_drv[12]~reg0.ACLR
xrst => com_drv[11]~reg0.ACLR
xrst => com_drv[10]~reg0.ACLR
xrst => com_drv[9]~reg0.ACLR
xrst => com_drv[8]~reg0.ACLR
xrst => com_drv[7]~reg0.ACLR
xrst => com_drv[6]~reg0.ACLR
xrst => com_drv[5]~reg0.ACLR
xrst => com_drv[4]~reg0.ACLR
xrst => com_drv[3]~reg0.ACLR
xrst => com_drv[2]~reg0.ACLR
xrst => com_drv[1]~reg0.ACLR
xrst => com_drv[0]~reg0.ACLR
xrst => com_drv[15]~reg0.ACLR
work => com_drv~44.OUTPUTSELECT
work => com_drv~45.OUTPUTSELECT
work => com_drv~46.OUTPUTSELECT
work => com_drv~47.OUTPUTSELECT
work => com_drv~48.OUTPUTSELECT
work => com_drv~49.OUTPUTSELECT
work => com_drv~50.OUTPUTSELECT
work => com_drv~51.OUTPUTSELECT
work => com_drv~52.OUTPUTSELECT
work => com_drv~53.OUTPUTSELECT
work => com_drv~54.OUTPUTSELECT
work => com_drv~55.OUTPUTSELECT
work => com_drv~56.OUTPUTSELECT
work => com_drv~57.OUTPUTSELECT
work => com_drv~58.OUTPUTSELECT
work => com_drv~59.OUTPUTSELECT
re => re~0.IN1
led_clk => led_clk~0.IN1
r_add[0] => r_add[0]~0.IN1
r_add[1] => com_drv~2.IN0
r_add[1] => com_drv~6.IN0
r_add[1] => com_drv~9.IN0
r_add[1] => com_drv~13.IN0
r_add[1] => com_drv~16.IN0
r_add[1] => com_drv~20.IN0
r_add[1] => com_drv~23.IN0
r_add[1] => com_drv~27.IN0
r_add[1] => com_drv~24.IN0
r_add[1] => com_drv~21.IN0
r_add[1] => com_drv~17.IN0
r_add[1] => com_drv~14.IN0
r_add[1] => com_drv~10.IN0
r_add[1] => com_drv~7.IN0
r_add[1] => com_drv~3.IN0
r_add[1] => com_drv~0.IN0
r_add[2] => com_drv~5.IN0
r_add[2] => com_drv~12.IN0
r_add[2] => com_drv~19.IN0
r_add[2] => com_drv~26.IN1
r_add[2] => com_drv~22.IN1
r_add[2] => com_drv~15.IN0
r_add[2] => com_drv~8.IN0
r_add[2] => com_drv~1.IN0
r_add[3] => com_drv~11.IN1
r_add[3] => com_drv~25.IN1
r_add[3] => com_drv~18.IN1
r_add[3] => com_drv~4.IN1
r_add[4] => com_drv~18.IN0
r_add[4] => com_drv~25.IN0
r_add[4] => com_drv~11.IN0
r_add[4] => com_drv~4.IN0
led_dc <= dc:comb_4.port4
red <= dc:comb_4.port5
com_drv[0] <= com_drv[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[1] <= com_drv[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[2] <= com_drv[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[3] <= com_drv[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[4] <= com_drv[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[5] <= com_drv[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[6] <= com_drv[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[7] <= com_drv[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[8] <= com_drv[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[9] <= com_drv[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[10] <= com_drv[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[11] <= com_drv[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[12] <= com_drv[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[13] <= com_drv[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[14] <= com_drv[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_drv[15] <= com_drv[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|xianshi|drive:comb_5|dc:comb_4
sclk => a.CLK
led_clk => a~0.IN1
led_clk => a~1.DATAB
re => led_dc~0.IN1
re => a~1.OUTPUTSELECT
r_add => led_dc~1.IN1
r_add => red~0.IN1
led_dc <= led_dc~1.DB_MAX_OUTPUT_PORT_TYPE
red <= red~0.DB_MAX_OUTPUT_PORT_TYPE


|xianshi|led_latcha:comb_6
sclk => red_data[14]~reg0.CLK
sclk => red_data[13]~reg0.CLK
sclk => red_data[12]~reg0.CLK
sclk => red_data[11]~reg0.CLK
sclk => red_data[10]~reg0.CLK
sclk => red_data[9]~reg0.CLK
sclk => red_data[8]~reg0.CLK
sclk => red_data[7]~reg0.CLK
sclk => red_data[6]~reg0.CLK
sclk => red_data[5]~reg0.CLK
sclk => red_data[4]~reg0.CLK
sclk => red_data[3]~reg0.CLK
sclk => red_data[2]~reg0.CLK
sclk => red_data[1]~reg0.CLK
sclk => red_data[0]~reg0.CLK
sclk => grn_data[15]~reg0.CLK
sclk => grn_data[14]~reg0.CLK
sclk => grn_data[13]~reg0.CLK
sclk => grn_data[12]~reg0.CLK
sclk => grn_data[11]~reg0.CLK
sclk => grn_data[10]~reg0.CLK
sclk => grn_data[9]~reg0.CLK
sclk => grn_data[8]~reg0.CLK
sclk => grn_data[7]~reg0.CLK
sclk => grn_data[6]~reg0.CLK
sclk => grn_data[5]~reg0.CLK
sclk => grn_data[4]~reg0.CLK
sclk => grn_data[3]~reg0.CLK
sclk => grn_data[2]~reg0.CLK
sclk => grn_data[1]~reg0.CLK
sclk => grn_data[0]~reg0.CLK
sclk => led_red[15].CLK
sclk => led_red[14].CLK
sclk => led_red[13].CLK
sclk => led_red[12].CLK
sclk => led_red[11].CLK
sclk => led_red[10].CLK
sclk => led_red[9].CLK
sclk => led_red[8].CLK
sclk => led_red[7].CLK
sclk => led_red[6].CLK
sclk => led_red[5].CLK
sclk => led_red[4].CLK
sclk => led_red[3].CLK
sclk => led_red[2].CLK
sclk => led_red[1].CLK
sclk => led_red[0].CLK
sclk => red_data[15]~reg0.CLK
xrst => red_data[14]~reg0.PRESET
xrst => red_data[13]~reg0.PRESET
xrst => red_data[12]~reg0.PRESET
xrst => red_data[11]~reg0.PRESET
xrst => red_data[10]~reg0.PRESET
xrst => red_data[9]~reg0.PRESET
xrst => red_data[8]~reg0.PRESET
xrst => red_data[7]~reg0.PRESET
xrst => red_data[6]~reg0.PRESET
xrst => red_data[5]~reg0.PRESET
xrst => red_data[4]~reg0.PRESET
xrst => red_data[3]~reg0.PRESET
xrst => red_data[2]~reg0.PRESET
xrst => red_data[1]~reg0.PRESET
xrst => red_data[0]~reg0.PRESET
xrst => grn_data[15]~reg0.PRESET
xrst => grn_data[14]~reg0.PRESET
xrst => grn_data[13]~reg0.PRESET
xrst => grn_data[12]~reg0.PRESET
xrst => grn_data[11]~reg0.PRESET
xrst => grn_data[10]~reg0.PRESET
xrst => grn_data[9]~reg0.PRESET
xrst => grn_data[8]~reg0.PRESET
xrst => grn_data[7]~reg0.PRESET
xrst => grn_data[6]~reg0.PRESET
xrst => grn_data[5]~reg0.PRESET
xrst => grn_data[4]~reg0.PRESET
xrst => grn_data[3]~reg0.PRESET
xrst => grn_data[2]~reg0.PRESET
xrst => grn_data[1]~reg0.PRESET
xrst => grn_data[0]~reg0.PRESET
xrst => red_data[15]~reg0.PRESET
xrst => led_red[15].ENA
xrst => led_red[14].ENA
xrst => led_red[13].ENA
xrst => led_red[12].ENA
xrst => led_red[11].ENA
xrst => led_red[10].ENA
xrst => led_red[9].ENA
xrst => led_red[8].ENA
xrst => led_red[7].ENA
xrst => led_red[6].ENA
xrst => led_red[5].ENA
xrst => led_red[4].ENA
xrst => led_red[3].ENA
xrst => led_red[2].ENA
xrst => led_red[1].ENA
xrst => led_red[0].ENA
led_dc => red_data~0.OUTPUTSELECT
led_dc => red_data~1.OUTPUTSELECT
led_dc => red_data~2.OUTPUTSELECT
led_dc => red_data~3.OUTPUTSELECT
led_dc => red_data~4.OUTPUTSELECT
led_dc => red_data~5.OUTPUTSELECT
led_dc => red_data~6.OUTPUTSELECT
led_dc => red_data~7.OUTPUTSELECT
led_dc => red_data~8.OUTPUTSELECT
led_dc => red_data~9.OUTPUTSELECT
led_dc => red_data~10.OUTPUTSELECT
led_dc => red_data~11.OUTPUTSELECT
led_dc => red_data~12.OUTPUTSELECT
led_dc => red_data~13.OUTPUTSELECT
led_dc => red_data~14.OUTPUTSELECT
led_dc => red_data~15.OUTPUTSELECT
led_dc => grn_data~0.OUTPUTSELECT
led_dc => grn_data~1.OUTPUTSELECT
led_dc => grn_data~2.OUTPUTSELECT
led_dc => grn_data~3.OUTPUTSELECT
led_dc => grn_data~4.OUTPUTSELECT
led_dc => grn_data~5.OUTPUTSELECT
led_dc => grn_data~6.OUTPUTSELECT
led_dc => grn_data~7.OUTPUTSELECT
led_dc => grn_data~8.OUTPUTSELECT
led_dc => grn_data~9.OUTPUTSELECT
led_dc => grn_data~10.OUTPUTSELECT
led_dc => grn_data~11.OUTPUTSELECT
led_dc => grn_data~12.OUTPUTSELECT
led_dc => grn_data~13.OUTPUTSELECT
led_dc => grn_data~14.OUTPUTSELECT
led_dc => grn_data~15.OUTPUTSELECT
red => led_red~0.OUTPUTSELECT
red => led_red~1.OUTPUTSELECT
red => led_red~2.OUTPUTSELECT
red => led_red~3.OUTPUTSELECT
red => led_red~4.OUTPUTSELECT
red => led_red~5.OUTPUTSELECT
red => led_red~6.OUTPUTSELECT
red => led_red~7.OUTPUTSELECT
red => led_red~8.OUTPUTSELECT
red => led_red~9.OUTPUTSELECT
red => led_red~10.OUTPUTSELECT
red => led_red~11.OUTPUTSELECT
red => led_red~12.OUTPUTSELECT
red => led_red~13.OUTPUTSELECT
red => led_red~14.OUTPUTSELECT
red => led_red~15.OUTPUTSELECT
red => red_data[15]~reg0.ENA
red => red_data[14]~reg0.ENA
red => red_data[13]~reg0.ENA
red => red_data[12]~reg0.ENA
red => red_data[11]~reg0.ENA
red => red_data[10]~reg0.ENA
red => red_data[9]~reg0.ENA
red => red_data[8]~reg0.ENA
red => red_data[7]~reg0.ENA
red => red_data[6]~reg0.ENA
red => red_data[5]~reg0.ENA
red => red_data[4]~reg0.ENA
red => red_data[3]~reg0.ENA
red => red_data[2]~reg0.ENA
red => red_data[1]~reg0.ENA
red => red_data[0]~reg0.ENA
red => grn_data[15]~reg0.ENA
red => grn_data[14]~reg0.ENA
red => grn_data[13]~reg0.ENA
red => grn_data[12]~reg0.ENA
red => grn_data[11]~reg0.ENA
red => grn_data[10]~reg0.ENA
red => grn_data[9]~reg0.ENA
red => grn_data[8]~reg0.ENA
red => grn_data[7]~reg0.ENA
red => grn_data[6]~reg0.ENA
red => grn_data[5]~reg0.ENA
red => grn_data[4]~reg0.ENA
red => grn_data[3]~reg0.ENA
red => grn_data[2]~reg0.ENA
red => grn_data[1]~reg0.ENA
red => grn_data[0]~reg0.ENA
r_data[0] => led_red~15.DATAB
r_data[0] => grn_data~15.DATAB
r_data[1] => led_red~14.DATAB
r_data[1] => grn_data~14.DATAB
r_data[2] => led_red~13.DATAB
r_data[2] => grn_data~13.DATAB
r_data[3] => led_red~12.DATAB
r_data[3] => grn_data~12.DATAB
r_data[4] => led_red~11.DATAB
r_data[4] => grn_data~11.DATAB
r_data[5] => led_red~10.DATAB
r_data[5] => grn_data~10.DATAB
r_data[6] => led_red~9.DATAB
r_data[6] => grn_data~9.DATAB
r_data[7] => led_red~8.DATAB
r_data[7] => grn_data~8.DATAB
r_data[8] => led_red~7.DATAB
r_data[8] => grn_data~7.DATAB
r_data[9] => led_red~6.DATAB
r_data[9] => grn_data~6.DATAB
r_data[10] => led_red~5.DATAB
r_data[10] => grn_data~5.DATAB
r_data[11] => led_red~4.DATAB
r_data[11] => grn_data~4.DATAB
r_data[12] => led_red~3.DATAB
r_data[12] => grn_data~3.DATAB
r_data[13] => led_red~2.DATAB
r_data[13] => grn_data~2.DATAB
r_data[14] => led_red~1.DATAB
r_data[14] => grn_data~1.DATAB
r_data[15] => led_red~0.DATAB
r_data[15] => grn_data~0.DATAB
red_data[0] <= red_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[1] <= red_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[2] <= red_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[3] <= red_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[4] <= red_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[5] <= red_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[6] <= red_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[7] <= red_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[8] <= red_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[9] <= red_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[10] <= red_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[11] <= red_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[12] <= red_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[13] <= red_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[14] <= red_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_data[15] <= red_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[0] <= grn_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[1] <= grn_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[2] <= grn_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[3] <= grn_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[4] <= grn_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[5] <= grn_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[6] <= grn_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[7] <= grn_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[8] <= grn_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[9] <= grn_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[10] <= grn_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[11] <= grn_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[12] <= grn_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[13] <= grn_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[14] <= grn_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
grn_data[15] <= grn_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE