xianshi.tan.summary

这是一个给予FPGA的动态显示代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 18.000 ns
From           : re
To             : drive:comb_5|com_drv[14]
From Clock     : --
To Clock       : sclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.300 ns
From           : led_latcha:comb_6|grn_data[0]
To             : grn_data[0]
From Clock     : sclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.300 ns
From           : work
To             : drive:comb_5|com_drv[15]
From Clock     : --
To Clock       : sclk
Failed Paths   : 0

Type           : Clock Setup: 'sclk'
Slack          : N/A
Required Time  : None
Actual Time    : 57.47 MHz ( period = 17.400 ns )
From           : drive:comb_5|dc:comb_4|a
To             : drive:comb_5|com_drv[14]
From Clock     : sclk
To Clock       : sclk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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