tim.v

来自「这是一个给予FPGA的动态显示代码」· Verilog 代码 · 共 25 行

module tim(sclk,xrst,led_clk);
input sclk,xrst;
output led_clk;
reg[8:0]a;
reg led_clk;
always@(posedge sclk or negedge xrst)
 begin
  if(xrst==1'b0)
    begin
      a<=9'b000000000;
    end
  else 
    begin
      a<=a+1'b1;
    end
 end
always@(posedge sclk)
 begin
   if(a==9'b111111110)
   led_clk<=1'b1;
   else
   led_clk<=1'b0;
 end
endmodule