📄 dss_isr_evm62_stub.lst
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4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 126 >> 1, regmask
4 .if (63 & 1)
4 .eval 0 + 1, BITCOUNT
4 .endif
4 .eval 63 >> 1, regmask
4 .if (31 & 1)
4 .eval 1 + 1, BITCOUNT
4 .endif
4 .eval 31 >> 1, regmask
4 .if (15 & 1)
4 .eval 2 + 1, BITCOUNT
4 .endif
4 .eval 15 >> 1, regmask
4 .if (7 & 1)
4 .eval 3 + 1, BITCOUNT
4 .endif
4 .eval 7 >> 1, regmask
4 .if (3 & 1)
4 .eval 4 + 1, BITCOUNT
4 .endif
4 .eval 3 >> 1, regmask
4 .if (1 & 1)
4 .eval 5 + 1, BITCOUNT
4 .endif
4 .eval 1 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 9
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 10
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
2 00000100 NUM_BITS cmask, c_bitcount
3 .asg 0, BITCOUNT
3 .eval 0, regmask
3 .loop 32
3 .if (regmask & 1)
3 .eval BITCOUNT + 1, BITCOUNT
3 .endif
3 .eval regmask >> 1, regmask
3 .endloop
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 11
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
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