📄 dss_isr_evm62_stub.lst
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2 000000f8 008003A2 mvc b0, csr ; globally enable interrupts
2 ; to allow nested interrupts
2
2 000000fc 01BC54F6 stw b3, *SP--[2] ; save old IER
2
1 ; Save user registers (except ISR registers)
1 00000100 C62_save C62_ABTEMPS & ~(C62_ISRAB), 0 & ~(C62_ISRC)
2 .asg 0, mask
2 .asg 0, bitn_a
2 .asg 0, bitn_b
2 .asg -1, bitn_c
2 .asg 0, bitn_0
2 .asg 0, bitn_1
2 .asg 0, bitn_next
2 .asg 0, bitcount
2 .asg 0, a_bitcount
2 .asg 0, b_bitcount
2 .asg 0, c_bitcount
2 .asg 0, creg0
2 .asg 0, creg1
2 .asg 0, creg_next
2
2 .eval C62_ABTEMPS & ~(C62_ISRAB) & 0x0000ffff, amask
2 .eval (C62_ABTEMPS & ~(C62_ISRAB) >> 16) & 0xffff, bmask
2 .eval 1008 & ~(C62_B15 >> 16), bmask ; don't save B15
2 .eval 0 & ~(C62_ISRC), cmask
2
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 5
2 .if (1020 = 0) & (1008 = 0) & (0 = 0)
2 .mexit
2 .endif
2
2 ;
2 ; Count 1 bits in masks
2 ;
2 00000100 NUM_BITS amask, a_bitcount
3 .asg 0, BITCOUNT
3 .eval 1020, regmask
3 .loop 32
3 .if (regmask & 1)
3 .eval BITCOUNT + 1, BITCOUNT
3 .endif
3 .eval regmask >> 1, regmask
3 .endloop
4 .if (1020 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 1020 >> 1, regmask
4 .if (510 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 510 >> 1, regmask
4 .if (255 & 1)
4 .eval 0 + 1, BITCOUNT
4 .endif
4 .eval 255 >> 1, regmask
4 .if (127 & 1)
4 .eval 1 + 1, BITCOUNT
4 .endif
4 .eval 127 >> 1, regmask
4 .if (63 & 1)
4 .eval 2 + 1, BITCOUNT
4 .endif
4 .eval 63 >> 1, regmask
4 .if (31 & 1)
4 .eval 3 + 1, BITCOUNT
4 .endif
4 .eval 31 >> 1, regmask
4 .if (15 & 1)
4 .eval 4 + 1, BITCOUNT
4 .endif
4 .eval 15 >> 1, regmask
4 .if (7 & 1)
4 .eval 5 + 1, BITCOUNT
4 .endif
4 .eval 7 >> 1, regmask
4 .if (3 & 1)
4 .eval 6 + 1, BITCOUNT
4 .endif
4 .eval 3 >> 1, regmask
4 .if (1 & 1)
4 .eval 7 + 1, BITCOUNT
4 .endif
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 6
4 .eval 1 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 7
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
2 00000100 NUM_BITS bmask, b_bitcount
3 .asg 0, BITCOUNT
3 .eval 1008, regmask
3 .loop 32
3 .if (regmask & 1)
3 .eval BITCOUNT + 1, BITCOUNT
3 .endif
3 .eval regmask >> 1, regmask
3 .endloop
4 .if (1008 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 1008 >> 1, regmask
4 .if (504 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 504 >> 1, regmask
4 .if (252 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 252 >> 1, regmask
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 8
4 .if (126 & 1)
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