📄 dss_isr_evm62_stub.lst
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TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 1
1 ; THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR
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50 ; You may not use the Program in non-TI devices.
51 ;
52 ; ======== dss_asm.s62 ========
53 ;
54 ;
55 .include c62.h62
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 2
A 1233
56 .include hwi.h62
57
58 .global _dss_isr_evm62_stub
59 .global _dss_isr_evm62_cisr
60
61 00000000 .text
62
63 ;
64 ; ======== _DSS_isr ========
65 ;
66 ; Calls the C ISR code
67 ;
68 00000000 _dss_isr_evm62_stub:
69
70 00000000 HWI_enter C62_ABTEMPS, 0, 0xffff, 0
1
1 00000000 HWI_enter_body IEMASK, CCMASK
2
2 00000000 CHK_nargs "HWI_enter", CCMASK
2 .if ($symcmp("", "error") = 0)
2 .emsg "HWI_enter CCMASK error"
2 .endif
2
2 ; Note: global interrupts disabled by C62xx on entry into ISR
2
2 ;
2 ; Handle switchover to ISR stack.
2 ;
2 ; WARNING: The following code has a few cases of software
2 ; pipelining, where a register is loaded with 'ldw' but the
2 ; old (pre-ldw) value is still used in the 'ldw' latency
2 ; slots.
2 ;
2 00000000 003C54F7 stw b0, *SP--[2]
2 00000004 0000002A! || mvkl _HWI_STKBOTTOM, b0 ; highest address
2 00000008 00BC22F7 stw b1, *+SP[1]
2 0000000c 0000006A! || mvkh _HWI_STKBOTTOM, b0
2
2 00000010 0001E8FA cmpgt SP, b0, b0
2 00000014 20000912 [ b0] b notOnHWIStack?
2 00000018 3080002A! [!b0] mvkl _HWI_STKTOP, b1 ; lowest address
2 0000001c 3080006A! [!b0] mvkh _HWI_STKTOP, b1
2 00000020 3085EAFA [!b0] cmplt SP, b1, b1
2 00000024 20BC01A2 [ b0] mv SP, b1 ; old b0 can be used safely here
2 00000028 27BC5D42 [ b0] addaw SP, 2, SP ; 2 = # words alloced by us
2
2 0000002c 50000892 [!b1] b onHWIStack?
2 00000030 50BC22E6 [!b1] ldw *+SP[1], b1 ; old b1 can be used for 4 more cycles
2 00000034 503C52E6 [!b1] ldw *++SP[2], b0 ; ld early, b0 used 3 cycles after br
2 00000038 00002000 nop 2
2 00000040 40BC01A3 [ b1] mv SP, b1
2 00000044 47BC5D42 ||[ b1] addaw SP, 2, SP ; 2 = # words alloced by us
2
2 00000048 notOnHWIStack?:
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 3
2 ;
2 ; The following operations below must be atomic:
2 ; SP = HWI_STKBOTTOM
2 ; HWI_D_spsave = SP
2 ;
2 00000048 000442E7 ldw *+b1[2], b0
2 0000004c 0000002A! || mvkl _HWI_D_spsave, b0
2 00000050 008422E7 ldw *+b1[1], b1
2 00000054 0000006A! || mvkh _HWI_D_spsave, b0
2 00000058 078002F7 stw SP, *b0 ; HWI_D_spsave = SP
2 0000005c 0780002A! || mvkl _HWI_STKBOTTOM, SP
2 00000060 0780006A! mvkh _HWI_STKBOTTOM, SP
2
2 ; no delay slots necessary to wait for above ldw's to
2 ; complete since b0, b1 aren't needed below for 2 more
2 ; cycles.
2
2 00000064 onHWIStack?:
2 ;
2 ; All GP registers are in their pre-interrupt state.
2 ;
2
2 ; Save ISR registers
2 00000064 07BD9DC2 subaw SP, HWI_NUMSTK, SP
2 00000068 003D42F5 stw a0, *+SP[HWI_STKA0] ; save A0
2 0000006c 003C11A0 || mv SP, a0 ; setup A-side stack pointer
2
2 00000070 003CA2F7 stw b0, *+SP[HWI_STKB0] ; B-side temp register save
2 00000074 00802275 || stw a1, *+a0[HWI_STKA1] ; A-side temp register save
2 00000078 008411A1 || mv b1, a1 ; setup B-side temp save
2 0000007c 009803E2 || mvc irp, b1 ; Save IRP return address
2
2 00000080 00808275 stw a1, *+a0[HWI_STKB1] ; actual save of B1
2 00000084 00BD02F7 || stw b1, *+SP[HWI_STKIRP] ; Save IRP/NRP return addr
2 00000088 008811A1 || mv b2, a1 ; setup B-side temp save
2 0000008c 010003E2 || mvc amr, b2 ; setup AMR save
2
2 00000090 01BC42F7 stw b3, *+SP[HWI_STKB3] ; save B3 return register
2 00000094 00806275 || stw a1, *+a0[HWI_STKB2] ; actual save of B2
2 00000098 008811A1 || mv b2, a1 ; setup AMR save
2 0000009c 007FFFAA || mvkl 0xffff, b0 ; setup mask
2
2 000000a0 0080E275 stw a1, *+a0[HWI_STKAMR] ; actual save of AMR
2 000000a4 073CC2F7 || stw DP, *+SP[HWI_STKDP]
2 000000a8 010420FB || zero b2 ; setup for AMR set
2 000000ac 0000006A || mvkh 0xffff, b0 ; setup mask
2
2 000000b0 0700002A! mvkl $bss, DP
2 000000b4 0700006A! mvkh $bss, DP
2
2 000000b8 000803A3 mvc b2, amr ; AMR = 0
2 000000bc 0080006C! || ldw *+DP(SWI_D_lock), a1 ; load SWI_D_lock
2
2 ; Disable maskable interrupts (no effect for NMIE)
2
TMS320C6x COFF Assembler Version 4.00 Fri Sep 15 10:24:27 2000
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_isr_evm62_stub.s62 PAGE 4
2 .if (0 = 0)
2 000000c0 0100006E! ldw *+DP(HWI_D_ccmask), b2 ; load HWI_D_ccmask
2 .else
2 .var CCMASKVAL
2 .asg 0, CCMASKVAL
2 .eval :CCMASK:, CCMASKVAL
2 mvk :CCMASKVAL:, b2 ; use the CCMASK value
2 .endif
2
2 000000c4 019003E3 mvc ier, b3 ; get current IER
2 000000c8 0003EDDA || xor -1, b0, b0 ; flip mask bits
2
2 000000cc 008C0F7B and b0, b3, b1 ; disable IEMASK bits
2 000000d0 000403E2 || mvc csr, b0 ; get CSR
2
2 000000d4 020403A3 mvc b1, ier ; set new IER
2 000000d8 003D22F7 || stw b0, *+SP[HWI_STKCSR] ; save CSR
2 000000dc 00002FDA || or GIE, b0, b0 ; turn on GIE of CSR
2
2 000000e0 00807E2B mvk C62_CCFIELDS, b1
2 000000e4 008421A0 || add a1, 1, a1 ; a1 = SWI_D_lock + 1
2 000000e8 008027E2 and b1, b0, b1 ; extract pcc+dcc fields of csr
2 000000ec 000022E2 xor b1, b0, b0 ; clear pcc+dcc fields of csr
2
2 000000f0 0080007D! stw a1, *+DP(SWI_D_lock) ; SWI_D_lock++
2 000000f4 000046E2 || or b2, b0, b0 ; change pcc and dcc fields
2
2
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