boot_c6727.asm

Configuring External Interrupts on TMS320C672x Devices

;* ------------------- File: boot_c6727.asm -----------------------------------*
            .title  "Flash bootup utility for C6727 EVM from DSP-Weuffen GmbH"

;************************************************************************
;* this file is based upon the file boot_c671x.s62 from spra999a.pdf/.zip from TI.
;* (C) 2006  DSP-Weuffen GmbH, Neuravensburg, GERMANY 
;************************************************************************

; comment in the below line when done with the EMIF and PLL init coding
EMIF_PLL_INIT_IS_DONE .set 1

; comment in the below line if you need to halt on startup
;WAIT_ON_STARTUP .set 1

; comment in the below line if you need to halt before finally launching the application
;WAIT_ON_FINALE .set 1



; set some global document options for assembler listing generation
            .option D,T
            .length 102
            .width  140

; global EMIF symbols defined for the c6727 family
            .include        c6727dsk.inc


; specify the section name and attributes for the below code
            .sect ".boot_load"
            .global _boot
            .global ___binit__



;************************************************************************
;* boot loader entry point
;************************************************************************
        .def _parallel_flash_signature

_boot2_handshake: ; reuse this memory locations after start
_parallel_flash_signature: ; this location has to be be loaded to IROM start (10000000h)
        .word TRANSFER_MAGIC_16 ; Magic number which tells the IROM-bootloader that the Flash width is 16Bit


;************************************************************************
;* boot loader entry point
;************************************************************************
_boot2_start_address: ; reuse this memory locations after start
_boot:  ; this location has to be be loaded to IROM start + 4 (10000004h)


        .if $isdefed("WAIT_ON_STARTUP")
;************************************************************************
;* DEBUG LOOP
;************************************************************************
        zero B2
_myloop1:
  [!B2] B _myloop1
        nop  5
_myloopend:
        nop
        .endif ; WAIT_ON_STARTUP


        .if $isdefed("EMIF_PLL_INIT_IS_DONE")
;************************************************************************
;* CONFIGURE EMIF
;************************************************************************

;   *(volatile unsigned char *)(EMIF_SDCR+3) = 0x80;          ; enter self-refresh mode
;   *(volatile unsigned int *)PLL_CSR  &= ~CSR_PLLEN;
;   *(volatile unsigned int *)PLL_CSR  &= ~CSR_PLLPWRDN;
;   /* Reset the pll.  PLL takes 125ns to reset. */
;   *(volatile unsigned int *)PLL_CSR  |= CSR_PLLRST;
        mvkl  PLL_CSR,A1
        mvkh  PLL_CSR,A1                    ; PLL_CSR
        ldw   *A1,A3
        mvkl  EMIF_SDCR+3,A0
        mvkh  EMIF_SDCR+3,A0
        mvkl  1000,B0                       ; Counter i
        mvkl  0x80,B1
        stw   B1,*A0
        mvkl  ~CSR_PLLEN,B1
        mvkh  ~CSR_PLLEN,B1
        and   A3,B1,A3
        stw   A3,*A1
        mvkl  ~CSR_PLLPWRDN,B1
        mvkh  ~CSR_PLLPWRDN,B1
        and   A3,B1,A3
        stw   A3,*A1
        mvkl  CSR_PLLRST,B1
        mvkh  CSR_PLLRST,B1
        or    A3,B1,A3
        stw   A3,*A1
        
;   {
;      register int i;
;      for(i=0;i<1000;i++) {}
;   }
PllDelay:     
   [b0] b  PllDelay
        sub   b0,1,b0
        nop   5
   
;  ------------------------------------------------------
;   PLLOUT = CLKIN/(DIV0+1) * PLLM                       
;   300    = 12/1 * 25                                   
;  ------------------------------------------------------
;  *(volatile unsigned int *)PLL_DIV0    = DIV_ENABLE + 0;
;  *(volatile unsigned int *)PLL_M       = 25;
        mvkl  DIV_ENABLE+0,B1
        mvkh  DIV_ENABLE+0,B1
        mvkl  PLL_DIV0,A0
        mvkh  PLL_DIV0,A0
        stw   b1,*a0
        mvkl  25,B1
        mvkh  25,B1
        mvkl  PLL_M,A0
        mvkh  PLL_M,A0
        stw   b1,*a0
;  ------------------------------------------------------
;   Program in reverse order.                            
;   DSP requires that pheriheral clocks be less then     
;   1/2 the CPU clock at all times.                      
;   Order not critical, since changes need GO to come into effect. 
;  ------------------------------------------------------
;  *(volatile unsigned int *)PLL_DIV3    = DIV_ENABLE + 2;
;  *(volatile unsigned int *)PLL_DIV2    = DIV_ENABLE + 1;
;  *(volatile unsigned int *)PLL_DIV1    = DIV_ENABLE + 0;
;  *(volatile unsigned int *)PLL_CMD     = CMD_GOSET;
;  *(volatile unsigned int *)PLL_CSR    &= ~CSR_PLLRST;
;  PLL_CSR &= RST 
        mvkl  DIV_ENABLE+2,B1
        mvkh  DIV_ENABLE+2,B1
        mvkl  PLL_DIV3,A0
        mvkh  PLL_DIV3,A0
        stw   b1,*a0
        mvkl  DIV_ENABLE+1,B1
        mvkh  DIV_ENABLE+1,B1
        mvkl  PLL_DIV2,A0
        mvkh  PLL_DIV2,A0
        stw   b1,*a0
        mvkl  DIV_ENABLE+0,B1
        mvkh  DIV_ENABLE+0,B1
        mvkl  PLL_DIV1,A0
        mvkh  PLL_DIV1,A0
        stw   b1,*a0
        mvkl  CMD_GOSET,B1
        mvkh  CMD_GOSET,B1
        ldw   *a1,A2
        mvkl  PLL_CMD,A0
        mvkh  PLL_CMD,A0
        stw   b1,*a0
        mvkl  ~CSR_PLLRST,B1
        mvkh  ~CSR_PLLRST,B1
        and   b1,a2,b1
        stw   b1,*a1

;  ------------------------------------------------------
;   Now enable pll path and we are off and running at    
;   300MHz with 100 MHz SDRAM.                           
;  ------------------------------------------------------
;  *(volatile unsigned int *)PLL_CSR |= CSR_PLLEN;
        mvkl  CSR_PLLEN,B2
        mvkh  CSR_PLLEN,B2
        or    b2,B1,b1
        stw   b1,*A1

;  *(volatile unsigned int *)EMIF_SDTIMR   = 0x31114610;
;  *(volatile unsigned int *)EMIF_SDSRETR  = 0x00000006;
;  *(volatile unsigned int *)EMIF_SDRCR    = 0x0000061a;
;  *(volatile unsigned int *)EMIF_SDCR     = 0x00000720;     ; 32Bit, CAS=2, 4 banks, 8 columns
;  *(volatile unsigned int *)EMIF_A1CR     = 0x886225bd;
        mvkl  EMIF_REG_START,A0
        mvkh  EMIF_REG_START,A0
        mvkl  0x31114610,B0
        mvkh  0x31114610,B0
        stw   B0,*+A0[(EMIF_SDTIMR-EMIF_REG_START)/4]
        mvkl  0x00000006,B0
        mvkh  0x00000006,B0
        stw   B0,*+A0[(EMIF_SDSRETR-EMIF_REG_START)/4]
        mvkl  0x0000061a,B0
        mvkh  0x0000061a,B0
        stw   B0,*+A0[(EMIF_SDRCR-EMIF_REG_START)/4]
        mvkl  0x00000720,B0
        mvkh  0x00000720,B0
        stw   B0,*+A0[(EMIF_SDCR-EMIF_REG_START)/4]
        mvkl  0x886225bd,B0
        mvkh  0x886225bd,B0
        stw   B0,*+A0[(EMIF_A1CR-EMIF_REG_START)/4]

        .endif ; EMIF_PLL_INIT_IS_DONE


;************************************************************************
; boot mode switch
; selects copy routine if either booting from parallel flash or from UHPI
;************************************************************************
            mvkl  CFGPIN1,A4          ; load address of cfgpin1 register
            mvkh  CFGPIN1,A4
            mvkl  CFGPIN1_nHCS, B3    ; load bitmask for /HCS bit
            mvkh  CFGPIN1_nHCS, B3