📄 c6727dsk.h
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/*******************************************************************************
* FILENAME
* c6x11dsk.h
*
* DESCRIPTION
* DSK Header File
*
*******************************************************************************/
#include "sysbasetypes.h"
void SetAddrLinesForFlash(U32 Adr);
void SetAddrHighLines(U32 Adr);
void InitEmif(void);
void InitGPIO(void);
void InitHPI(void);
void InitPll(void);
void ResetPll(void);
void SetAddrToFlash(void);
void SetAddrToExpansion(void);
void SetAddrToControlRegister(void);
/* Start address of peripherals */
#define INTERNAL_ROM_PAGE_0 0X00000000 // Start: Internal ROM Page 0 (256K Bytes) End: 0x0003FFFF Byte and Word
#define INTERNAL_ROM PAGE_1 0x00040000 // Start: Internal ROM Page 1 (128K Bytes) End: 0x0005FFFF Byte and Word
#define INTERNAL_RAM_PAGE_0 0x10000000 // Start: Internal RAM Page 0 (256K Bytes) End: 0x1003FFFF Byte and Word
#define MEMORY_N_CACHE_CONTROL_REG_START 0x20000000 // Start: Memory and Cache Control Registers End: 0x2000001F Word Only
#define EMULATION_CONTROL_REG_START 0x30000000 // Start: Emulation Control Registers (Do Not Access) End: 0x3FFFFFFF Word Only
#define DEVICE_CONFIG_REG_START 0x40000000 // Start: Device Configuration Registers End: 0x40000083 Word Only
#define PLL_REG_START 0x41000000 // Start: PLL Control Registers End: 0x4100015F Word Only
#define RTI_REG_START 0x42000000 // Start: Real-time Interrupt (RTI) Control Registers End: 0x420000A3 Word Only
#define UHPI_REG_START 0x43000000 // Start: Universal Host-Port Interface (UHPI) Registers End: 0x43000043 Word Only
#define McASP0_REG_START 0x44000000 // Start: McASP0 Control Registers End: 0x440002BF Word Only
#define McASP1_REG_START 0x45000000 // Start: McASP1 Control Registers End: 0x450002BF Word Only
#define McASP2_REG_START 0x46000000 // Start: McASP2 Control Registers End: 0x460002BF Word Only
#define SPI0_REG_START 0x47000000 // Start: SPI0 Control Registers End: 0x4700007F Word Only
#define SPI1_REG_START 0x48000000 // Start: SPI1 Control Registers End: 0x4800007F Word Only
#define I2C0_REG_START 0x49000000 // Start: I2C0 Control Registers End: 0x4900007F Word Only
#define I2C1_REG_START 0x4A000000 // Start: I2C1 Control Registers End: 0x4A00007F Word Only
#define McASP0_DMA_REG_START 0x54000000 // Start: McASP0 DMA Port (any address in this range) End: 0x54FFFFFF Word Only
#define McASP1_DMA_REG_START 0x55000000 // Start: McASP1 DMA Port (any address in this range) End: 0x55FFFFFF Word Only
#define McASP2_DMA_REG_START 0x56000000 // Start: McASP2 DMA Port (any address in this range) End: 0x56FFFFFF Word Only
#define dMAX_REG_START 0x60000000 // Start: dMAX Control Registers End: 0x6000008F Word Only
#define MAX0_EVENT_ENTRY 0x61008000 // Start: MAX0 (HiMAX) Event Entry Table End: 0x6100807F Byte and Word
#define MAX0_TRANSFER_ENTRY 0x610080A0 // Start: MAX0 (HiMAX) Transfer Entry Table End: 0x610081FF Byte and Word
#define MAX1_EVENT_ENTRY 0x62008000 // Start: MAX1 (LoMAX) Event Entry Table End: 0x6200807F Byte and Word
#define MAX1_TRANSFER_ENTRY 0x620080A0 // Start: MAX1 (LoMAX) Transfer Entry Table End: 0x620081FF Byte and Word
#define SDRAM_SPACE_START 0x80000000 // Start: External SDRAM space on EMIF End: 0x8FFFFFFF Byte and Word
#define FLASH_SPACE_START 0x90000000 // Start: External Asynchronous / Flash space on EMIF End: 0x9FFFFFFF Byte and Word
#define EMIF_REG_START 0xF0000000 // Start: EMIF Control Registers End: 0xF00000BF Word Only(
/* Definitions for the DSK Board and SW */
#define PI 3.1415926
#define IRAM_SIZE 0x00040000
#define SDRAM_SIZE 0x01000000
#define EXPANSION_SIZE 0x00008000
#define INT_VECTAB_SIZE 0x0200 /* length of vector table in byte */
#define INTERNAL_MEM_START (INTERNAL_RAM_PAGE_0+0x10000) /* about something after prog */
#define INTERNAL_MEM_SIZE IRAM_SIZE-0x10000 /* 256kByte (incl. 512Byte VEC */
#define EXTERNAL_MEM_START SDRAM_SPACE_START /* CE2 SDRAM area */
#define EXTERNAL_MEM_SIZE SDRAM_SIZE /* 16MByte SDRAM */
/* Flash definitions */
#define FLASH_SIZE 0x80000
#define FLASH_WRITE_SIZE 0x80
#define FLASH_START FLASH_SPACE_START
#define FLASH_END (FLASH_SPACE_START+FLASH_SIZE)
#define FLASH_ADR1 0x90005555
#define FLASH_ADR2 0x90002AAA
#define FLASH_KEY1 0xAA
#define FLASH_KEY2 0x55
#define FLASH_KEY3 0xA0
#define ALL_A 0xaaaaaaaa
#define ALL_5 0x55555555
#define ALT_A5 0xa5a5a5a5
#define ALT_5A 0x5a5a5a5a
#define CE1_8 0xffffff03 /* reg to set CE1 as 8bit async */
#define CE1_32 0xffffff23 /* reg to set CE1 as 32bit async */
/* CPLD definitions */
#define CPLD_RW_REGISTER (FLASH_SPACE_START + 0x000000) // Flash address to read/write for internal register
#define CPLD_SET_FLASH (FLASH_SPACE_START + 0x000000) // Flash
#define CPLD_SET_EXPANSION (FLASH_SPACE_START + 0x400000) // Expansion
#define CPLD_SET_REGISTER (FLASH_SPACE_START + 0x600000) // CPLD Register
#define CPLD_SET_DEACTIVATE (FLASH_SPACE_START + 0x700000) // Deactivate CPLD
/* C6727 peripheral definitions */
#define MCASP0_PFUNC (volatile unsigned int *)(McASP0_REG_START + 0x10)
#define MCASP0_PDIR (volatile unsigned int *)(McASP0_REG_START + 0x14)
#define MCASP0_PDOUT (volatile unsigned int *)(McASP0_REG_START + 0x18)
#define MCASP0_PDIN (volatile unsigned int *)(McASP0_REG_START + 0x1c)
#define MCASP0_PDSET (volatile unsigned int *)(McASP0_REG_START + 0x1c)
#define MCASP0_PDCLR (volatile unsigned int *)(McASP0_REG_START + 0x20)
#define MCASP1_PFUNC (volatile unsigned int *)(McASP1_REG_START + 0x10)
#define MCASP1_PDIR (volatile unsigned int *)(McASP1_REG_START + 0x14)
#define MCASP1_PDOUT (volatile unsigned int *)(McASP1_REG_START + 0x18)
#define MCASP1_PDIN (volatile unsigned int *)(McASP1_REG_START + 0x1c)
#define MCASP1_PDSET (volatile unsigned int *)(McASP1_REG_START + 0x1c)
#define MCASP1_PDCLR (volatile unsigned int *)(McASP1_REG_START + 0x20)
#define MCASP2_PFUNC (volatile unsigned int *)(McASP2_REG_START + 0x10)
#define MCASP2_PDIR (volatile unsigned int *)(McASP2_REG_START + 0x14)
#define MCASP2_PDOUT (volatile unsigned int *)(McASP2_REG_START + 0x18)
#define MCASP2_PDIN (volatile unsigned int *)(McASP2_REG_START + 0x1c)
#define MCASP2_PDSET (volatile unsigned int *)(McASP2_REG_START + 0x1c)
#define MCASP2_PDCLR (volatile unsigned int *)(McASP2_REG_START + 0x20)
#define PLL_BASE_ADDR PLL_REG_START
#define PLL_PID ( PLL_BASE_ADDR + 0x000 ) // identification
#define PLL_CSR ( PLL_BASE_ADDR + 0x100 ) // control/status
#define PLL_M ( PLL_BASE_ADDR + 0x110 ) // multiplier 1...25
#define PLL_DIV0 ( PLL_BASE_ADDR + 0x114 ) //
#define PLL_DIV1 ( PLL_BASE_ADDR + 0x118 ) //
#define PLL_DIV2 ( PLL_BASE_ADDR + 0x11C ) //
#define PLL_DIV3 ( PLL_BASE_ADDR + 0x120 ) //
#define PLL_CMD ( PLL_BASE_ADDR + 0x138 ) // controller command
#define PLL_STAT ( PLL_BASE_ADDR + 0x13c ) // controller status
#define ALN_CTL ( PLL_BASE_ADDR + 0x140 ) // controller clock align control
#define CKEN ( PLL_BASE_ADDR + 0x148 ) // clock enable control
#define CKSTAT ( PLL_BASE_ADDR + 0x14c ) // clock status
#define SYSTAT ( PLL_BASE_ADDR + 0x150 ) // SYSCLK status
#define CSR_PLLEN 0x00000001
#define CSR_PLLPWRDN 0x00000010
#define CSR_OSCPWRDN 0x00000004
#define CSR_PLLRST 0x00000008
#define CSR_PLLPWRDN 0x00000010
#define CSR_PLLSTABLE 0x00000040
#define DIV_ENABLE 0x00008000
#define CMD_GOSET 0x00000001
#define EMIF_AWCCR (EMIF_REG_START + 0x04) // async wait cycle config
#define EMIF_SDCR (EMIF_REG_START + 0x08) // SDRAM config reg
#define EMIF_SDRCR (EMIF_REG_START + 0x0c) // SDRAM refresh control
#define EMIF_A1CR (EMIF_REG_START + 0x10) // asynchronous 1 config
#define EMIF_SDTIMR (EMIF_REG_START + 0x20) // SDRAM timing register
#define EMIF_SDSRETR (EMIF_REG_START + 0x3c) // SDRAM self refresh exit timing register
#define EMIF_EIRR (EMIF_REG_START + 0x40) // interrupt raw
#define EMIF_EIMR (EMIF_REG_START + 0x44) // interrupt mask reg
#define EMIF_EIMSR (EMIF_REG_START + 0x48) // interrupt mask set
#define EMIF_EIMCR (EMIF_REG_START + 0x4c) // interrupt mask clear reg
#define UHPI (volatile unsigned int *)(UHPI_REG_START+0x08) // Configuration Register
#define CFGHPIAMSB (volatile unsigned int *)(UHPI_REG_START+0x0C) // Most Significant Byte of UHPI Address
#define CFGHPIAUMB (volatile unsigned int *)(UHPI_REG_START+0x10) // Upper Middle Byte of UHPI Address
/* UHPI Internal Registers */
#define PID (volatile unsigned int *)(UHPI_REG_START+0x00) // Peripheral ID Register
#define PWREMU (volatile unsigned int *)(UHPI_REG_START+0x04) // Power and Emulation Management Register
#define GPIOINT (volatile unsigned int *)(UHPI_REG_START+0x08) // General Purpose I/O Interrupt Control Register
#define GPIOEN (volatile unsigned int *)(UHPI_REG_START+0x0C) // General Purpose I/O Enable Register
#define GPIODIR1 (volatile unsigned int *)(UHPI_REG_START+0x10) // General Purpose I/O Direction Register 1
#define GPIODAT1 (volatile unsigned int *)(UHPI_REG_START+0x14) // General Purpose I/O Data Register 1
#define GPIODIR2 (volatile unsigned int *)(UHPI_REG_START+0x18) // General Purpose I/O Direction Register 2
#define GPIODAT2 (volatile unsigned int *)(UHPI_REG_START+0x1C) // General Purpose I/O Data Register 2
#define GPIODIR3 (volatile unsigned int *)(UHPI_REG_START+0x20) // General Purpose I/O Direction Register 3
#define GPIODAT3 (volatile unsigned int *)(UHPI_REG_START+0x24) // General Purpose I/O Data Register 3
#define HPIC (volatile unsigned int *)(UHPI_REG_START+0x30) // Control Register
#define HPIAW (volatile unsigned int *)(UHPI_REG_START+0x34) // Write Address Register
#define HPIAR (volatile unsigned int *)(UHPI_REG_START+0x38) // Read Address Register
#define UHPI_BYTEAD (1<<4) // 0 R/W UHPI Host Address Type
// 0 = Host Address is a word address
// 1 = Host Address is a byte address
#define UHPI_FULL (1<<3) // 0 R/W UHPI Multiplexing Mode (when NMUX = 0)
// 0 = Half-Word (16-bit data) Multiplexed Host Address and Data Mode
// 1 = Fullword (32-bit data) Multiplexed Host Address and Data Mode
#define UHPI_NMUX (1<<2) // 0 R/W UHPI Non-Multiplexed Mode Enable
// 0 = Multiplexed Host Address and Data Mode
// 1 = Non-Multiplexed Host Address and Data Mode (utilizes optional
// UHPI_HA[15:0] pins). Host data bus is 32 bits in Non-Multiplexed mode.
#define UHPI_PAGEM (1<<1) // 0 R/W UHPI Page Mode Enable (Only for Multiplexed Host Address and Data Mode).
// 0 = Full 32-bit DSP address specified through host port.
// 1 = Only lower 16 bits of DSP address are specified through host port. Upper
// 16 bits are restricted to the page selected by CFGHPIAMSB and
// CFGHPIAUMB registers.
#define UHPI_ENA (1<<0) // 0 R/W UHPI Enable
// 0 = UHPI is disabled
// 1 = UHPI is enabled. Set this bit to '1' only after configuring the other bits in this
// register.
//
#define UHPI_HPIAMSB (1<<0) // R/W UHPI most significant byte of DSP address to access in non-multiplexed host
// address/data mode and in multiplexed host address and data mode when
// CFGHPI.PAGEM = 1. Sets bits [31:24] of the DSP internal address as
// accessed through UHPI.
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