📄 cslr_uhpi.h
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#define CSL_HPI_GPIO_DIR2_DIR3_MASK (0x00000008u)
#define CSL_HPI_GPIO_DIR2_DIR3_SHIFT (0x00000003u)
#define CSL_HPI_GPIO_DIR2_DIR3_RESETVAL (0x00000000u)
/*----DIR3 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR3_INPUT (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR3_OUTPUT (0x00000001u)
#define CSL_HPI_GPIO_DIR2_DIR2_MASK (0x00000004u)
#define CSL_HPI_GPIO_DIR2_DIR2_SHIFT (0x00000002u)
#define CSL_HPI_GPIO_DIR2_DIR2_RESETVAL (0x00000000u)
/*----DIR2 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR2_INPUT (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR2_OUTPUT (0x00000001u)
#define CSL_HPI_GPIO_DIR2_DIR1_MASK (0x00000002u)
#define CSL_HPI_GPIO_DIR2_DIR1_SHIFT (0x00000001u)
#define CSL_HPI_GPIO_DIR2_DIR1_RESETVAL (0x00000000u)
/*----DIR1 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR1_INPUT (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR1_OUTPUT (0x00000001u)
#define CSL_HPI_GPIO_DIR2_DIR0_MASK (0x00000001u)
#define CSL_HPI_GPIO_DIR2_DIR0_SHIFT (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR0_RESETVAL (0x00000000u)
/*----DIR0 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR0_INPUT (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR0_OUTPUT (0x00000001u)
#define CSL_HPI_GPIO_DIR2_RESETVAL (0x00000000u)
/* GPIO_DAT2 */
#define CSL_HPI_GPIO_DAT2_DAT14_MASK (0x00004000u)
#define CSL_HPI_GPIO_DAT2_DAT14_SHIFT (0x0000000Eu)
#define CSL_HPI_GPIO_DAT2_DAT14_RESETVAL (0x00000000u)
/*----DAT14 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT14_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT14_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT13_MASK (0x00002000u)
#define CSL_HPI_GPIO_DAT2_DAT13_SHIFT (0x0000000Du)
#define CSL_HPI_GPIO_DAT2_DAT13_RESETVAL (0x00000000u)
/*----DAT13 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT13_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT13_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT12_MASK (0x00001000u)
#define CSL_HPI_GPIO_DAT2_DAT12_SHIFT (0x0000000Cu)
#define CSL_HPI_GPIO_DAT2_DAT12_RESETVAL (0x00000000u)
/*----DAT12 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT12_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT12_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT11_MASK (0x00000800u)
#define CSL_HPI_GPIO_DAT2_DAT11_SHIFT (0x0000000Bu)
#define CSL_HPI_GPIO_DAT2_DAT11_RESETVAL (0x00000000u)
/*----DAT11 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT11_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT11_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT10_MASK (0x00000400u)
#define CSL_HPI_GPIO_DAT2_DAT10_SHIFT (0x0000000Au)
#define CSL_HPI_GPIO_DAT2_DAT10_RESETVAL (0x00000000u)
/*----DAT10 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT10_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT10_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT9_MASK (0x00000200u)
#define CSL_HPI_GPIO_DAT2_DAT9_SHIFT (0x00000009u)
#define CSL_HPI_GPIO_DAT2_DAT9_RESETVAL (0x00000000u)
/*----DAT9 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT9_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT9_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT8_MASK (0x00000100u)
#define CSL_HPI_GPIO_DAT2_DAT8_SHIFT (0x00000008u)
#define CSL_HPI_GPIO_DAT2_DAT8_RESETVAL (0x00000000u)
/*----DAT8 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT8_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT8_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT7_MASK (0x00000080u)
#define CSL_HPI_GPIO_DAT2_DAT7_SHIFT (0x00000007u)
#define CSL_HPI_GPIO_DAT2_DAT7_RESETVAL (0x00000000u)
/*----DAT7 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT7_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT7_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT6_MASK (0x00000040u)
#define CSL_HPI_GPIO_DAT2_DAT6_SHIFT (0x00000006u)
#define CSL_HPI_GPIO_DAT2_DAT6_RESETVAL (0x00000000u)
/*----DAT6 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT6_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT6_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT5_MASK (0x00000020u)
#define CSL_HPI_GPIO_DAT2_DAT5_SHIFT (0x00000005u)
#define CSL_HPI_GPIO_DAT2_DAT5_RESETVAL (0x00000000u)
/*----DAT5 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT5_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT5_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT4_MASK (0x00000010u)
#define CSL_HPI_GPIO_DAT2_DAT4_SHIFT (0x00000004u)
#define CSL_HPI_GPIO_DAT2_DAT4_RESETVAL (0x00000000u)
/*----DAT4 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT4_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT4_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT3_MASK (0x00000008u)
#define CSL_HPI_GPIO_DAT2_DAT3_SHIFT (0x00000003u)
#define CSL_HPI_GPIO_DAT2_DAT3_RESETVAL (0x00000000u)
/*----DAT3 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT3_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT3_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT2_MASK (0x00000004u)
#define CSL_HPI_GPIO_DAT2_DAT2_SHIFT (0x00000002u)
#define CSL_HPI_GPIO_DAT2_DAT2_RESETVAL (0x00000000u)
/*----DAT2 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT2_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT2_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT1_MASK (0x00000002u)
#define CSL_HPI_GPIO_DAT2_DAT1_SHIFT (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT1_RESETVAL (0x00000000u)
/*----DAT1 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT1_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT1_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT0_MASK (0x00000001u)
#define CSL_HPI_GPIO_DAT2_DAT0_SHIFT (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT0_RESETVAL (0x00000000u)
/*----DAT0 Tokens----*/
#define CSL_HPI_GPIO_DAT2_DAT0_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_DAT2_DAT0_ENABLE (0x00000001u)
#define CSL_HPI_GPIO_DAT2_RESETVAL (0x00000000u)
/* GPIO_DIR3 */
#define CSL_HPI_GPIO_DIR3_DIR31_MASK (0x80000000u)
#define CSL_HPI_GPIO_DIR3_DIR31_SHIFT (0x0000001Fu)
#define CSL_HPI_GPIO_DIR3_DIR31_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR30_MASK (0x40000000u)
#define CSL_HPI_GPIO_DIR3_DIR30_SHIFT (0x0000001Eu)
#define CSL_HPI_GPIO_DIR3_DIR30_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR29_MASK (0x20000000u)
#define CSL_HPI_GPIO_DIR3_DIR29_SHIFT (0x0000001Du)
#define CSL_HPI_GPIO_DIR3_DIR29_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR28_MASK (0x10000000u)
#define CSL_HPI_GPIO_DIR3_DIR28_SHIFT (0x0000001Cu)
#define CSL_HPI_GPIO_DIR3_DIR28_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR27_MASK (0x08000000u)
#define CSL_HPI_GPIO_DIR3_DIR27_SHIFT (0x0000001Bu)
#define CSL_HPI_GPIO_DIR3_DIR27_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR26_MASK (0x04000000u)
#define CSL_HPI_GPIO_DIR3_DIR26_SHIFT (0x0000001Au)
#define CSL_HPI_GPIO_DIR3_DIR26_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR25_MASK (0x02000000u)
#define CSL_HPI_GPIO_DIR3_DIR25_SHIFT (0x00000019u)
#define CSL_HPI_GPIO_DIR3_DIR25_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR24_MASK (0x01000000u)
#define CSL_HPI_GPIO_DIR3_DIR24_SHIFT (0x00000018u)
#define CSL_HPI_GPIO_DIR3_DIR24_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR23_MASK (0x00800000u)
#define CSL_HPI_GPIO_DIR3_DIR23_SHIFT (0x00000017u)
#define CSL_HPI_GPIO_DIR3_DIR23_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR22_MASK (0x00400000u)
#define CSL_HPI_GPIO_DIR3_DIR22_SHIFT (0x00000016u)
#define CSL_HPI_GPIO_DIR3_DIR22_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR21_MASK (0x00200000u)
#define CSL_HPI_GPIO_DIR3_DIR21_SHIFT (0x00000015u)
#define CSL_HPI_GPIO_DIR3_DIR21_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR20_MASK (0x00100000u)
#define CSL_HPI_GPIO_DIR3_DIR20_SHIFT (0x00000014u)
#define CSL_HPI_GPIO_DIR3_DIR20_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR19_MASK (0x00080000u)
#define CSL_HPI_GPIO_DIR3_DIR19_SHIFT (0x00000013u)
#define CSL_HPI_GPIO_DIR3_DIR19_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR18_MASK (0x00040000u)
#define CSL_HPI_GPIO_DIR3_DIR18_SHIFT (0x00000012u)
#define CSL_HPI_GPIO_DIR3_DIR18_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR17_MASK (0x00020000u)
#define CSL_HPI_GPIO_DIR3_DIR17_SHIFT (0x00000011u)
#define CSL_HPI_GPIO_DIR3_DIR17_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR16_MASK (0x00010000u)
#define CSL_HPI_GPIO_DIR3_DIR16_SHIFT (0x00000010u)
#define CSL_HPI_GPIO_DIR3_DIR16_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR15_MASK (0x00008000u)
#define CSL_HPI_GPIO_DIR3_DIR15_SHIFT (0x0000000Fu)
#define CSL_HPI_GPIO_DIR3_DIR15_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR14_MASK (0x00004000u)
#define CSL_HPI_GPIO_DIR3_DIR14_SHIFT (0x0000000Eu)
#define CSL_HPI_GPIO_DIR3_DIR14_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR13_MASK (0x00002000u)
#define CSL_HPI_GPIO_DIR3_DIR13_SHIFT (0x0000000Du)
#define CSL_HPI_GPIO_DIR3_DIR13_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR12_MASK (0x00001000u)
#define CSL_HPI_GPIO_DIR3_DIR12_SHIFT (0x0000000Cu)
#define CSL_HPI_GPIO_DIR3_DIR12_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR11_MASK (0x00000800u)
#define CSL_HPI_GPIO_DIR3_DIR11_SHIFT (0x0000000Bu)
#define CSL_HPI_GPIO_DIR3_DIR11_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR10_MASK (0x00000400u)
#define CSL_HPI_GPIO_DIR3_DIR10_SHIFT (0x0000000Au)
#define CSL_HPI_GPIO_DIR3_DIR10_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR9_MASK (0x00000200u)
#define CSL_HPI_GPIO_DIR3_DIR9_SHIFT (0x00000009u)
#define CSL_HPI_GPIO_DIR3_DIR9_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR8_MASK (0x00000100u)
#define CSL_HPI_GPIO_DIR3_DIR8_SHIFT (0x00000008u)
#define CSL_HPI_GPIO_DIR3_DIR8_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR7_MASK (0x00000080u)
#define CSL_HPI_GPIO_DIR3_DIR7_SHIFT (0x00000007u)
#define CSL_HPI_GPIO_DIR3_DIR7_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR6_MASK (0x00000040u)
#define CSL_HPI_GPIO_DIR3_DIR6_SHIFT (0x00000006u)
#define CSL_HPI_GPIO_DIR3_DIR6_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR5_MASK (0x00000020u)
#define CSL_HPI_GPIO_DIR3_DIR5_SHIFT (0x00000005u)
#define CSL_HPI_GPIO_DIR3_DIR5_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR4_MASK (0x00000010u)
#define CSL_HPI_GPIO_DIR3_DIR4_SHIFT (0x00000004u)
#define CSL_HPI_GPIO_DIR3_DIR4_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR3_MASK (0x00000008u)
#define CSL_HPI_GPIO_DIR3_DIR3_SHIFT (0x00000003u)
#define CSL_HPI_GPIO_DIR3_DIR3_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR2_MASK (0x00000004u)
#define CSL_HPI_GPIO_DIR3_DIR2_SHIFT (0x00000002u)
#define CSL_HPI_GPIO_DIR3_DIR2_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR1_MASK (0x00000002u)
#define CSL_HPI_GPIO_DIR3_DIR1_SHIFT (0x00000001u)
#define CSL_HPI_GPIO_DIR3_DIR1_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR0_MASK (0x00000001u)
#define CSL_HPI_GPIO_DIR3_DIR0_SHIFT (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR0_RESETVAL (0x00000000u)
/*----DIR Tokens----*/
#define CSL_HPI_GPIO_DIR3_DIR_INPUT (0x00000000u)
#define CSL_HPI_GPIO_DIR3_DIR_OUTPUT (0x00000001u)
#define CSL_HPI_GPIO_DIR3_RESETVAL (0x00000000u)
/* GPIO_DAT3 */
#define CSL_HPI_GPIO_DAT3_DAT31_MASK (0x80000000u)
#define CSL_HPI_GPIO_DAT3_DAT31_SHIFT (0x0000001Fu)
#define CSL_HPI_GPIO_DAT3_DAT31_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT30_MASK (0x40000000u)
#define CSL_HPI_GPIO_DAT3_DAT30_SHIFT (0x0000001Eu)
#define CSL_HPI_GPIO_DAT3_DAT30_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT29_MASK (0x20000000u)
#define CSL_HPI_GPIO_DAT3_DAT29_SHIFT (0x0000001Du)
#define CSL_HPI_GPIO_DAT3_DAT29_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT28_MASK (0x10000000u)
#define CSL_HPI_GPIO_DAT3_DAT28_SHIFT (0x0000001Cu)
#define CSL_HPI_GPIO_DAT3_DAT28_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT27_MASK (0x08000000u)
#define CSL_HPI_GPIO_DAT3_DAT27_SHIFT (0x0000001Bu)
#define CSL_HPI_GPIO_DAT3_DAT27_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT26_MASK (0x04000000u)
#define CSL_HPI_GPIO_DAT3_DAT26_SHIFT (0x0000001Au)
#define CSL_HPI_GPIO_DAT3_DAT26_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT25_MASK (0x02000000u)
#define CSL_HPI_GPIO_DAT3_DAT25_SHIFT (0x00000019u)
#define CSL_HPI_GPIO_DAT3_DAT25_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT24_MASK (0x01000000u)
#define CSL_HPI_GPIO_DAT3_DAT24_SHIFT (0x00000018u)
#define CSL_HPI_GPIO_DAT3_DAT24_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT23_MASK (0x00800000u)
#define CSL_HPI_GPIO_DAT3_DAT23_SHIFT (0x00000017u)
#define CSL_HPI_GPIO_DAT3_DAT23_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT22_MASK (0x00400000u)
#define CSL_HPI_GPIO_DAT3_DAT22_SHIFT (0x00000016u)
#define CSL_HPI_GPIO_DAT3_DAT22_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT21_MASK (0x00200000u)
#define CSL_HPI_GPIO_DAT3_DAT21_SHIFT (0x00000015u)
#define CSL_HPI_GPIO_DAT3_DAT21_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT20_MASK (0x00100000u)
#define CSL_HPI_GPIO_DAT3_DAT20_SHIFT (0x00000014u)
#define CSL_HPI_GPIO_DAT3_DAT20_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT19_MASK (0x00080000u)
#define CSL_HPI_GPIO_DAT3_DAT19_SHIFT (0x00000013u)
#define CSL_HPI_GPIO_DAT3_DAT19_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT18_MASK (0x00040000u)
#define CSL_HPI_GPIO_DAT3_DAT18_SHIFT (0x00000012u)
#define CSL_HPI_GPIO_DAT3_DAT18_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT17_MASK (0x00020000u)
#define CSL_HPI_GPIO_DAT3_DAT17_SHIFT (0x00000011u)
#define CSL_HPI_GPIO_DAT3_DAT17_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT16_MASK (0x00010000u)
#define CSL_HPI_GPIO_DAT3_DAT16_SHIFT (0x00000010u)
#define CSL_HPI_GPIO_DAT3_DAT16_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT15_MASK (0x00008000u)
#define CSL_HPI_GPIO_DAT3_DAT15_SHIFT (0x0000000Fu)
#define CSL_HPI_GPIO_DAT3_DAT15_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT14_MASK (0x00004000u)
#define CSL_HPI_GPIO_DAT3_DAT14_SHIFT (0x0000000Eu)
#define CSL_HPI_GPIO_DAT3_DAT14_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT13_MASK (0x00002000u)
#define CSL_HPI_GPIO_DAT3_DAT13_SHIFT (0x0000000Du)
#define CSL_HPI_GPIO_DAT3_DAT13_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT12_MASK (0x00001000u)
#define CSL_HPI_GPIO_DAT3_DAT12_SHIFT (0x0000000Cu)
#define CSL_HPI_GPIO_DAT3_DAT12_RESETVAL (0x00000000u)
#define CSL_HPI_GPIO_DAT3_DAT11_MASK (0x00000800u)
#define CSL_HPI_GPIO_DAT3_DAT11_SHIFT (0x0000000Bu)
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