cslr_uhpi.h

Configuring External Interrupts on TMS320C672x Devices

#ifndef _CSLR_HPI_H_
#define _CSLR_HPI_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_hpi.h
 * 
 * \brief This file contains the Register Desciptions for HPI
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PWREMU_MGMT;
    volatile Uint32 GPINT_CTRL;
    volatile Uint32 GPIO_EN;
    volatile Uint32 GPIO_DIR1;
    volatile Uint32 GPIO_DAT1;
    volatile Uint32 GPIO_DIR2;
    volatile Uint32 GPIO_DAT2;
    volatile Uint32 GPIO_DIR3;
    volatile Uint32 GPIO_DAT3;
    volatile Uint32 RSVD0[2];
    volatile Uint32 HPIC;
    volatile Uint32 HPIAW;
    volatile Uint32 HPIAR;
} CSL_HpiRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_HPI_PID_TYPE_MASK            (0x00FF0000u)
#define CSL_HPI_PID_TYPE_SHIFT           (0x00000010u)
#define CSL_HPI_PID_TYPE_RESETVAL        (0x00000001u)

#define CSL_HPI_PID_CLASS_MASK           (0x0000FF00u)
#define CSL_HPI_PID_CLASS_SHIFT          (0x00000008u)
#define CSL_HPI_PID_CLASS_RESETVAL       (0x00000002u)

#define CSL_HPI_PID_REV_MASK             (0x000000FFu)
#define CSL_HPI_PID_REV_SHIFT            (0x00000000u)
#define CSL_HPI_PID_REV_RESETVAL         (0x00000002u)

#define CSL_HPI_PID_RESETVAL             (0x00010202u)

/* PWREMU_MGMT */

#define CSL_HPI_PWREMU_MGMT_SOFT_MASK    (0x00000002u)
#define CSL_HPI_PWREMU_MGMT_SOFT_SHIFT   (0x00000001u)
#define CSL_HPI_PWREMU_MGMT_SOFT_RESETVAL (0x00000000u)

/*----SOFT Tokens----*/
#define CSL_HPI_PWREMU_MGMT_SOFT_OFF     (0x00000000u)
#define CSL_HPI_PWREMU_MGMT_SOFT_ON      (0x00000001u)

#define CSL_HPI_PWREMU_MGMT_FREE_MASK    (0x00000001u)
#define CSL_HPI_PWREMU_MGMT_FREE_SHIFT   (0x00000000u)
#define CSL_HPI_PWREMU_MGMT_FREE_RESETVAL (0x00000000u)

/*----FREE Tokens----*/
#define CSL_HPI_PWREMU_MGMT_FREE_OFF     (0x00000000u)
#define CSL_HPI_PWREMU_MGMT_FREE_ON      (0x00000001u)

#define CSL_HPI_PWREMU_MGMT_RESETVAL     (0x00000000u)

/* GPINT_CTRL */

#define CSL_HPI_GPINT_CTRL_GPINT_INV2_MASK (0x00040000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV2_SHIFT (0x00000012u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV2_RESETVAL (0x00000000u)

/*----GPINT_INV2 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_INV2_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV2_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_GPINT_INV1_MASK (0x00020000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV1_SHIFT (0x00000011u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV1_RESETVAL (0x00000000u)

/*----GPINT_INV1 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_INV1_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV1_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_GPINT_INV0_MASK (0x00010000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV0_SHIFT (0x00000010u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV0_RESETVAL (0x00000000u)

/*----GPINT_INV0 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_INV0_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_INV0_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_GPINT_EN2_MASK (0x00000004u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN2_SHIFT (0x00000002u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN2_RESETVAL (0x00000000u)

/*----GPINT_EN2 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_EN2_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN2_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_GPINT_EN1_MASK (0x00000002u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN1_SHIFT (0x00000001u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN1_RESETVAL (0x00000000u)

/*----GPINT_EN1 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_EN1_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN1_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_GPINT_EN0_MASK (0x00000001u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN0_SHIFT (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN0_RESETVAL (0x00000000u)

/*----GPINT_EN0 Tokens----*/
#define CSL_HPI_GPINT_CTRL_GPINT_EN0_DISABLE (0x00000000u)
#define CSL_HPI_GPINT_CTRL_GPINT_EN0_ENABLE (0x00000001u)

#define CSL_HPI_GPINT_CTRL_RESETVAL      (0x00000000u)

/* GPIO_EN */

#define CSL_HPI_GPIO_EN_GPIO_EN16_MASK   (0x00010000u)
#define CSL_HPI_GPIO_EN_GPIO_EN16_SHIFT  (0x00000010u)
#define CSL_HPI_GPIO_EN_GPIO_EN16_RESETVAL (0x00000000u)

/*----GPIO_EN16 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN16_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN16_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN15_MASK   (0x00008000u)
#define CSL_HPI_GPIO_EN_GPIO_EN15_SHIFT  (0x0000000Fu)
#define CSL_HPI_GPIO_EN_GPIO_EN15_RESETVAL (0x00000000u)

/*----GPIO_EN15 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN15_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN15_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN14_MASK   (0x00004000u)
#define CSL_HPI_GPIO_EN_GPIO_EN14_SHIFT  (0x0000000Eu)
#define CSL_HPI_GPIO_EN_GPIO_EN14_RESETVAL (0x00000000u)

/*----GPIO_EN14 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN14_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN14_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN13_MASK   (0x00002000u)
#define CSL_HPI_GPIO_EN_GPIO_EN13_SHIFT  (0x0000000Du)
#define CSL_HPI_GPIO_EN_GPIO_EN13_RESETVAL (0x00000000u)

/*----GPIO_EN13 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN13_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN13_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN12_MASK   (0x00001000u)
#define CSL_HPI_GPIO_EN_GPIO_EN12_SHIFT  (0x0000000Cu)
#define CSL_HPI_GPIO_EN_GPIO_EN12_RESETVAL (0x00000000u)

/*----GPIO_EN12 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN12_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN12_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN11_MASK   (0x00000800u)
#define CSL_HPI_GPIO_EN_GPIO_EN11_SHIFT  (0x0000000Bu)
#define CSL_HPI_GPIO_EN_GPIO_EN11_RESETVAL (0x00000000u)

/*----GPIO_EN11 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN11_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN11_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN10_MASK   (0x00000400u)
#define CSL_HPI_GPIO_EN_GPIO_EN10_SHIFT  (0x0000000Au)
#define CSL_HPI_GPIO_EN_GPIO_EN10_RESETVAL (0x00000000u)

/*----GPIO_EN10 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN10_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN10_ENABLE (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN9_MASK    (0x00000200u)
#define CSL_HPI_GPIO_EN_GPIO_EN9_SHIFT   (0x00000009u)
#define CSL_HPI_GPIO_EN_GPIO_EN9_RESETVAL (0x00000000u)

/*----GPIO_EN9 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN9_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN9_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN8_MASK    (0x00000100u)
#define CSL_HPI_GPIO_EN_GPIO_EN8_SHIFT   (0x00000008u)
#define CSL_HPI_GPIO_EN_GPIO_EN8_RESETVAL (0x00000000u)

/*----GPIO_EN8 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN8_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN8_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN7_MASK    (0x00000080u)
#define CSL_HPI_GPIO_EN_GPIO_EN7_SHIFT   (0x00000007u)
#define CSL_HPI_GPIO_EN_GPIO_EN7_RESETVAL (0x00000000u)

/*----GPIO_EN7 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN7_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN7_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN6_MASK    (0x00000040u)
#define CSL_HPI_GPIO_EN_GPIO_EN6_SHIFT   (0x00000006u)
#define CSL_HPI_GPIO_EN_GPIO_EN6_RESETVAL (0x00000000u)

/*----GPIO_EN6 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN6_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN6_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN5_MASK    (0x00000020u)
#define CSL_HPI_GPIO_EN_GPIO_EN5_SHIFT   (0x00000005u)
#define CSL_HPI_GPIO_EN_GPIO_EN5_RESETVAL (0x00000000u)

/*----GPIO_EN5 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN5_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN5_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN4_MASK    (0x00000010u)
#define CSL_HPI_GPIO_EN_GPIO_EN4_SHIFT   (0x00000004u)
#define CSL_HPI_GPIO_EN_GPIO_EN4_RESETVAL (0x00000000u)

/*----GPIO_EN4 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN4_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN4_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN3_MASK    (0x00000008u)
#define CSL_HPI_GPIO_EN_GPIO_EN3_SHIFT   (0x00000003u)
#define CSL_HPI_GPIO_EN_GPIO_EN3_RESETVAL (0x00000000u)

/*----GPIO_EN3 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN3_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN3_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN2_MASK    (0x00000004u)
#define CSL_HPI_GPIO_EN_GPIO_EN2_SHIFT   (0x00000002u)
#define CSL_HPI_GPIO_EN_GPIO_EN2_RESETVAL (0x00000000u)

/*----GPIO_EN2 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN2_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN2_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN1_MASK    (0x00000002u)
#define CSL_HPI_GPIO_EN_GPIO_EN1_SHIFT   (0x00000001u)
#define CSL_HPI_GPIO_EN_GPIO_EN1_RESETVAL (0x00000000u)

/*----GPIO_EN1 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN1_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN1_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_GPIO_EN0_MASK    (0x00000001u)
#define CSL_HPI_GPIO_EN_GPIO_EN0_SHIFT   (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN0_RESETVAL (0x00000000u)

/*----GPIO_EN0 Tokens----*/
#define CSL_HPI_GPIO_EN_GPIO_EN0_DISABLE (0x00000000u)
#define CSL_HPI_GPIO_EN_GPIO_EN0_ENABLE  (0x00000001u)

#define CSL_HPI_GPIO_EN_RESETVAL         (0x00000000u)

/* GPIO_DIR1 */

#define CSL_HPI_GPIO_DIR1_DIR_MASK       (0xFFFFFFFFu)
#define CSL_HPI_GPIO_DIR1_DIR_SHIFT      (0x00000000u)
#define CSL_HPI_GPIO_DIR1_DIR_RESETVAL   (0x00000000u)

/*----DIR Tokens----*/
#define CSL_HPI_GPIO_DIR1_DIR_INPUT      (0x00000000u)
#define CSL_HPI_GPIO_DIR1_DIR_OUTPUT     (0x00000001u)

#define CSL_HPI_GPIO_DIR1_RESETVAL       (0x00000000u)

/* GPIO_DAT1 */

#define CSL_HPI_GPIO_DAT1_DAT_MASK       (0xFFFFFFFFu)
#define CSL_HPI_GPIO_DAT1_DAT_SHIFT      (0x00000000u)
#define CSL_HPI_GPIO_DAT1_DAT_RESETVAL   (0x00000000u)

#define CSL_HPI_GPIO_DAT1_RESETVAL       (0x00000000u)

/* GPIO_DIR2 */

#define CSL_HPI_GPIO_DIR2_DIR14_MASK     (0x00004000u)
#define CSL_HPI_GPIO_DIR2_DIR14_SHIFT    (0x0000000Eu)
#define CSL_HPI_GPIO_DIR2_DIR14_RESETVAL (0x00000000u)

/*----DIR14 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR14_INPUT    (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR14_OUTPUT   (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR13_MASK     (0x00002000u)
#define CSL_HPI_GPIO_DIR2_DIR13_SHIFT    (0x0000000Du)
#define CSL_HPI_GPIO_DIR2_DIR13_RESETVAL (0x00000000u)

/*----DIR13 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR13_INPUT    (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR13_OUTPUT   (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR12_MASK     (0x00001000u)
#define CSL_HPI_GPIO_DIR2_DIR12_SHIFT    (0x0000000Cu)
#define CSL_HPI_GPIO_DIR2_DIR12_RESETVAL (0x00000000u)

/*----DIR12 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR12_INPUT    (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR12_OUTPUT   (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR11_MASK     (0x00000800u)
#define CSL_HPI_GPIO_DIR2_DIR11_SHIFT    (0x0000000Bu)
#define CSL_HPI_GPIO_DIR2_DIR11_RESETVAL (0x00000000u)

/*----DIR11 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR11_INPUT    (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR11_OUTPUT   (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR10_MASK     (0x00000400u)
#define CSL_HPI_GPIO_DIR2_DIR10_SHIFT    (0x0000000Au)
#define CSL_HPI_GPIO_DIR2_DIR10_RESETVAL (0x00000000u)

/*----DIR10 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR10_INPUT    (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR10_OUTPUT   (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR9_MASK      (0x00000200u)
#define CSL_HPI_GPIO_DIR2_DIR9_SHIFT     (0x00000009u)
#define CSL_HPI_GPIO_DIR2_DIR9_RESETVAL  (0x00000000u)

/*----DIR9 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR9_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR9_OUTPUT    (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR8_MASK      (0x00000100u)
#define CSL_HPI_GPIO_DIR2_DIR8_SHIFT     (0x00000008u)
#define CSL_HPI_GPIO_DIR2_DIR8_RESETVAL  (0x00000000u)

/*----DIR8 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR8_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR8_OUTPUT    (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR7_MASK      (0x00000080u)
#define CSL_HPI_GPIO_DIR2_DIR7_SHIFT     (0x00000007u)
#define CSL_HPI_GPIO_DIR2_DIR7_RESETVAL  (0x00000000u)

/*----DIR7 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR7_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR7_OUTPUT    (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR6_MASK      (0x00000040u)
#define CSL_HPI_GPIO_DIR2_DIR6_SHIFT     (0x00000006u)
#define CSL_HPI_GPIO_DIR2_DIR6_RESETVAL  (0x00000000u)

/*----DIR6 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR6_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR6_OUTPUT    (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR5_MASK      (0x00000020u)
#define CSL_HPI_GPIO_DIR2_DIR5_SHIFT     (0x00000005u)
#define CSL_HPI_GPIO_DIR2_DIR5_RESETVAL  (0x00000000u)

/*----DIR5 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR5_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR5_OUTPUT    (0x00000001u)

#define CSL_HPI_GPIO_DIR2_DIR4_MASK      (0x00000010u)
#define CSL_HPI_GPIO_DIR2_DIR4_SHIFT     (0x00000004u)
#define CSL_HPI_GPIO_DIR2_DIR4_RESETVAL  (0x00000000u)

/*----DIR4 Tokens----*/
#define CSL_HPI_GPIO_DIR2_DIR4_INPUT     (0x00000000u)
#define CSL_HPI_GPIO_DIR2_DIR4_OUTPUT    (0x00000001u)