csl_rti.h

Configuring External Interrupts on TMS320C672x Devices

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/** ============================================================================
 *   @file  csl_rti.h
 *
 *   @path  $(CSLPATH)\soc\c67\src
 *
 *   @desc  API header file for Real Time Interrupt CSL
 *
 */ 
 
/* =============================================================================
 *  Revision History
 *  ===============
 * 2-Dec-2004 Sd File Created.
 * 25-Oct-2005 sd Comments added for query CSL_RTI_QUERY_CUR_UC0_CNT
 *
 * =============================================================================
 */
 
#ifndef _CSL_RTI_H_
#define _CSL_RTI_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <cslr_rti.h>
#include <soc.h>

/* enable/disable the RTI Digital watchdog */
#define CSL_RTI_DWD_ENABLE  0xACED5312 
#define CSL_RTI_DWD_DISABLE 0x5312ACED

/* key values to set digital watchdog*/
#define CSL_RTI_WDKEY1  0xE51A
#define CSL_RTI_WDKEY2  0xA35C

/**
 *  Enumeration for Start/Continue Counters when device in debug mode
 */
typedef enum {
    /** Stop the Counters in debug mode */
    CSL_RTI_COUNTERS_STOP = 0,
    /** Continue the counters in debug mode */
    CSL_RTI_COUNTERS_RUN = 1
} CSL_RtiContOnSuspend;

/**
 *  Enumeration for Configure external interrupt source for both UC0 and FRC0
 *  and Configure external interrupt source for both UC1 and FRC1.
 */
typedef enum {
    /** Enable capture event triggered by Capture Event Source 0 */
    CSL_RTI_CAPTURE_EVENT_SOURCE0 = 0,
    /** Enable capture event triggered by Capture Event Source 1 */
    CSL_RTI_CAPTURE_EVENT_SOURCE1 = 1
} CSL_RtiExtnControl;

/**
 * Enumeration for free running counters with which
 * compare registers value is compared.
 */
typedef enum {
    /** Enable compare with FRC0 */
    CSL_RTI_FRC0_COMPARE_ENABLE = 0,
    /** enable compare with FRC1 */
    CSL_RTI_FRC1_COMPARE_ENABLE = 1
} CSL_RtiCompareCntl;

/** 
 *  This will have the base-address information for the peripheral
 *  instance
 */
typedef struct {
    /** Base-address of the Configuration registers of the peripheral */
    CSL_RtiRegsOvly regs;
} CSL_RtiBaseAddress;

/** 
 *  Module specific parameters. Present implementation doesn't have
 *  any module specific parameters.
 */
typedef struct {
   /** 
    *   Bit mask to be used for module specific parameters.
    *  The below declaration is just a place-holder for future
    *  implementation.
    */
    CSL_BitMask16   flags;
} CSL_RtiParam;

/** 
 *  Module specific context information. Present implementation doesn't
 *  have any Context information.
 */

typedef struct {
   /** 
    *  Context information of Real Time Interrupt.
    *  The below declaration is just a place-holder for future
    *  implementation.
    */
    Uint16  contextInfo;
} CSL_RtiContext;

/** 
 * Enumeration for hardware control commands
 */
typedef enum {
   /**
    * @brief    Start the Block0 Counters
    * @param   (None)
    */
    CSL_RTI_CMD_START_BLOCK0            = 0,
   /**
    * @brief    Stop the Block0 Counters
    * @param    (None)
    */
    CSL_RTI_CMD_STOP_BLOCK0             = 1,
   /**
    * @brief    Start the Block1 Counters
    * @param    (None)
    */
    CSL_RTI_CMD_START_BLOCK1            = 2,
   /**
    * @brief    Stop the Block1 Counters
    * @param    (None)
    */
    CSL_RTI_CMD_STOP_BLOCK1             = 3,
   /**
    * @brief    Clear the Compare Interrupt0
    * @param (None)
    */
    CSL_RTI_CMD_CLEAR_INT0              = 4,
   /**
    * @brief    Clear the Compare Interrupt1
    * @param (None)
    */
    CSL_RTI_CMD_CLEAR_INT1              = 5,
   /**
    * @brief    Clear the Compare Interrupt2
    * @param    (None)
    */
    CSL_RTI_CMD_CLEAR_INT2              = 6,
   /**
    * @brief    Clear the Compare Interrupt3
    * @param    (None)
    */
    CSL_RTI_CMD_CLEAR_INT3              = 7,
   /**
    * @brief    Clear the Overflow Interrupt0
    * @param    (None)
    */
    CSL_RTI_CMD_CLEAR_OVFINT0           = 8,
   /**
    * @brief    Clear the Overflow Interrupt1
    * @param    (None)
    */
    CSL_RTI_CMD_CLEAR_OVFINT1           = 9,
   /**
    * @brief    Enable Digital Watchdog 
    * @param    (None)
    */
    CSL_RTI_CMD_DWD_ENABLE              = 10,
   /**
    * @brief    Disable Digital Watchdog 
    * @param    (None)
    */
    CSL_RTI_CMD_DWD_DISABLE             = 11,
   /**
    * @brief    Clear Digital Watchdog status
    * @param    (None)
    */
    CSL_RTI_CMD_CLEAR_DWD               = 12,    
   /**
    * @brief    Set the Digital Watchdog Key
    * @param    (None)
    */
    CSL_RTI_CMD_WDKEY                   = 13
    
}   CSL_RtiHwControlCmd;

/**
 *  Enumeration for hardware status query commands
 */
typedef enum {
   /**
    * @brief   Query the current value of free running counter0
    * @param   (Uint32 *)
    */
    CSL_RTI_QUERY_CUR_FRC0_CNT          = 0,
   /**
    * @brief    Query the current value of up counter0
	* 			Reading the Free running counter before the Up counter read
	*           is taken care by this query.
	*           [NB: Up counter value is updated by a previous read of the 
	*			Free Running Counter]
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_CUR_UC0_CNT           = 1,
   /**
    * @brief    Query the current value of free running counter1
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_CUR_FRC1_CNT          = 2,
   /**
    * @brief    Query the current value of up counter1
	* 			Reading the Free running counter before the Up counter read
	*           is taken care by this query.
	*           [NB: Up counter value is updated by a previous read of the 
	*			Free Running Counter]
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_CUR_UC1_CNT           = 3,
   /**
    * @brief    Query the captured value of up counter0
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_UC0_CAPTURE_VAL       = 4,
   /**
    * @brief    Query the captured value of free running counter0
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_FRC0_CAPTURE_VAL      = 5,
   /**
    * @brief    Query the captured value of up counter1
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_UC1_CAPTURE_VAL       = 6,
   /**
    * @brief    Query the captured value of free running counter1
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_FRC1_CAPTURE_VAL      = 7,
   /**
    * @brief    Query the value of compare0 register
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_COMP0_CNT             = 8,
   /**
    * @brief    Query the value of compare1 register
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_COMP1_CNT             = 9,
   /**
    * @brief    Query the value of compare2 register
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_COMP2_CNT             = 10,
   /**
    * @brief    Query the value of compare3 register
    * @param    (Uint32 *)
    */  
    CSL_RTI_QUERY_COMP3_CNT             = 11,
   /**
    * @brief    Query the Status of overflow interrupt0
    * @param    (Bool *)
    */  
    CSL_RTI_QUERY_OVLINT0_STATUS        = 12,
   /**
    * @brief    Query the Status of overflow interrupt1
    * @param    (Bool *)
    */  
    CSL_RTI_QUERY_OVLINT1_STATUS        = 13,
   /**
    * @brief    Query the Status of compare interrupt0
    * @param    (Bool *)
    */  
    CSL_RTI_QUERY_INT0_STATUS           = 14,
   /**
    * @brief    Query the Status of compare interrupt1
    * @param    (Bool *)
    */
    CSL_RTI_QUERY_INT1_STATUS           = 15,
   /**
    * @brief    Query the Status of compare interrupt2
    * @param    (Bool *)
    */
    CSL_RTI_QUERY_INT2_STATUS           = 16,
   /**
    * @brief    Query the Status of compare interrupt3
    * @param    (Bool *)
    */
    CSL_RTI_QUERY_INT3_STATUS           = 17,
   /**
    * @brief    Query the Status of digital watchdog
    * @param    (Bool *)
    */
    CSL_RTI_QUERY_WATCHDOG_STATUS       = 18,
   /**
    * @brief    Query the digital watchdog Counter value
    * @param    (Uint32 *)
    */
    CSL_RTI_QUERY_WATCHDOG_DWNCTR       = 19
}   CSL_RtiHwStatusQuery;

/**
 * This structure is used to set compare up counter values.
 */
typedef struct {
    /** set Compare up counter0 value */
    Uint32 compareUpCntr0;
    /** set Compare up counter1 value */
    Uint32 compareUpCntr1;
} CSL_RtiCompUpCounter;

/** 
 * This structure is used to set Up counters and Free running counters values.
 */
typedef struct {
    /** Set Free Running Counter0 value */
    Uint32 frc0Counter;
    /** Set Up Counter0 value */
    Uint32 uc0Counter;
    /** Set Free Running Counter1 value */
    Uint32 frc1Counter;
    /** Set Up Counter1 value */
    Uint32 uc1Counter;
} CSL_RtiCounters;

/** 
 * This structure is used to set Compare register values.
 */
typedef struct {
    /** Set Compare0 value */
    Uint32 comp0Val;
    /** Set Compare1 value */
    Uint32 comp1Val;
    /** Set Compare2 value */
    Uint32 comp2Val;
    /** Set Compare3 value */
    Uint32 comp3Val;
} CSL_RtiCompareVal;

/** 
 * This structure is used to set Update Compare register values.
 */
typedef struct {
    /** Set Update Compare0 value */
    Uint32 updateComp0Val;
    /** Set Update Compare1 value */
    Uint32 updateComp1Val;
    /** Set Update Compare2 value */
    Uint32 updateComp2Val;
    /** Set Update Compare3 value */
    Uint32 updateComp3Val;
} CSL_RtiUpdateCompVal;

/** 
 * This structure is used enable/disable the DMA requests.
 */