cslr_mcasp.h

Configuring External Interrupts on TMS320C672x Devices

#ifndef _CSLR_MCASP_H_
#define _CSLR_MCASP_H_
/*********************************************************************
 * Copyright (C) 2003-2005 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_mcasp.h
 * 
 * \brief This file contains the Register Desciptions for McASP
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PWRDEMU;
    volatile Uint32 RSVD0[2];
    volatile Uint32 PFUNC;
    volatile Uint32 PDIR;
    volatile Uint32 PDOUT;
    volatile Uint32 PDIN_PDSET;
    volatile Uint32 PDCLR;
    volatile Uint32 RSVD1[8];
    volatile Uint32 GBLCTL;
    volatile Uint32 AMUTE;
    volatile Uint32 DLBCTL;
    volatile Uint32 DITCTL;
    volatile Uint32 RSVD2[3];
    volatile Uint32 RGBLCTL;
    volatile Uint32 RMASK;
    volatile Uint32 RFMT;
    volatile Uint32 AFSRCTL;
    volatile Uint32 ACLKRCTL;
    volatile Uint32 AHCLKRCTL;
    volatile Uint32 RTDM;
    volatile Uint32 RINTCTL;
    volatile Uint32 RSTAT;
    volatile Uint32 RSLOT;
    volatile Uint32 RCLKCHK;
    volatile Uint32 REVTCTL;
    volatile Uint32 RSVD3[4];
    volatile Uint32 XGBLCTL;
    volatile Uint32 XMASK;
    volatile Uint32 XFMT;
    volatile Uint32 AFSXCTL;
    volatile Uint32 ACLKXCTL;
    volatile Uint32 AHCLKXCTL;
    volatile Uint32 XTDM;
    volatile Uint32 XINTCTL;
    volatile Uint32 XSTAT;
    volatile Uint32 XSLOT;
    volatile Uint32 XCLKCHK;
    volatile Uint32 XEVTCTL;
    volatile Uint32 RSVD4[12];
    volatile Uint32 DITCSRA0;
    volatile Uint32 DITCSRA1;
    volatile Uint32 DITCSRA2;
    volatile Uint32 DITCSRA3;
    volatile Uint32 DITCSRA4;
    volatile Uint32 DITCSRA5;
    volatile Uint32 DITCSRB0;
    volatile Uint32 DITCSRB1;
    volatile Uint32 DITCSRB2;
    volatile Uint32 DITCSRB3;
    volatile Uint32 DITCSRB4;
    volatile Uint32 DITCSRB5;
    volatile Uint32 DITUDRA0;
    volatile Uint32 DITUDRA1;
    volatile Uint32 DITUDRA2;
    volatile Uint32 DITUDRA3;
    volatile Uint32 DITUDRA4;
    volatile Uint32 DITUDRA5;
    volatile Uint32 DITUDRB0;
    volatile Uint32 DITUDRB1;
    volatile Uint32 DITUDRB2;
    volatile Uint32 DITUDRB3;
    volatile Uint32 DITUDRB4;
    volatile Uint32 DITUDRB5;
    volatile Uint32 RSVD5[8];
    volatile Uint32 SRCTL0;
    volatile Uint32 SRCTL1;
    volatile Uint32 SRCTL2;
    volatile Uint32 SRCTL3;
    volatile Uint32 SRCTL4;
    volatile Uint32 SRCTL5;
    volatile Uint32 SRCTL6;
    volatile Uint32 SRCTL7;
    volatile Uint32 SRCTL8;
    volatile Uint32 SRCTL9;
    volatile Uint32 SRCTL10;
    volatile Uint32 SRCTL11;
    volatile Uint32 SRCTL12;
    volatile Uint32 SRCTL13;
    volatile Uint32 SRCTL14;
    volatile Uint32 SRCTL15;
    volatile Uint32 RSVD6[16];
    volatile Uint32 XBUF0;
    volatile Uint32 XBUF1;
    volatile Uint32 XBUF2;
    volatile Uint32 XBUF3;
    volatile Uint32 XBUF4;
    volatile Uint32 XBUF5;
    volatile Uint32 XBUF6;
    volatile Uint32 XBUF7;
    volatile Uint32 XBUF8;
    volatile Uint32 XBUF9;
    volatile Uint32 XBUF10;
    volatile Uint32 XBUF11;
    volatile Uint32 XBUF12;
    volatile Uint32 XBUF13;
    volatile Uint32 XBUF14;
    volatile Uint32 XBUF15;
    volatile Uint32 RSVD7[16];
    volatile Uint32 RBUF0;
    volatile Uint32 RBUF1;
    volatile Uint32 RBUF2;
    volatile Uint32 RBUF3;
    volatile Uint32 RBUF4;
    volatile Uint32 RBUF5;
    volatile Uint32 RBUF6;
    volatile Uint32 RBUF7;
    volatile Uint32 RBUF8;
    volatile Uint32 RBUF9;
    volatile Uint32 RBUF10;
    volatile Uint32 RBUF11;
    volatile Uint32 RBUF12;
    volatile Uint32 RBUF13;
    volatile Uint32 RBUF14;
    volatile Uint32 RBUF15;
} CSL_McaspRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_MCASP_PID_TYPE_MASK          (0x00FF0000u)
#define CSL_MCASP_PID_TYPE_SHIFT         (0x00000010u)
#define CSL_MCASP_PID_TYPE_RESETVAL      (0x00000010u)

#define CSL_MCASP_PID_CLASS_MASK         (0x0000FF00u)
#define CSL_MCASP_PID_CLASS_SHIFT        (0x00000008u)
#define CSL_MCASP_PID_CLASS_RESETVAL     (0x00000001u)

#define CSL_MCASP_PID_REV_MASK           (0x000000FFu)
#define CSL_MCASP_PID_REV_SHIFT          (0x00000000u)
#define CSL_MCASP_PID_REV_RESETVAL       (0x00000001u)

#define CSL_MCASP_PID_RESETVAL           (0x00100101u)

/* PWRDEMU */

#define CSL_MCASP_PWRDEMU_FREE_MASK      (0x00000001u)
#define CSL_MCASP_PWRDEMU_FREE_SHIFT     (0x00000000u)
#define CSL_MCASP_PWRDEMU_FREE_RESETVAL  (0x00000000u)

/*----FREE Tokens----*/
#define CSL_MCASP_PWRDEMU_FREE_OFF       (0x00000000u)
#define CSL_MCASP_PWRDEMU_FREE_ON        (0x00000001u)

#define CSL_MCASP_PWRDEMU_RESETVAL       (0x00000000u)

/* PFUNC */

#define CSL_MCASP_PFUNC_AFSR_MASK        (0x80000000u)
#define CSL_MCASP_PFUNC_AFSR_SHIFT       (0x0000001Fu)
#define CSL_MCASP_PFUNC_AFSR_RESETVAL    (0x00000000u)

/*----AFSR Tokens----*/
#define CSL_MCASP_PFUNC_AFSR_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AFSR_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AHCLKR_MASK      (0x40000000u)
#define CSL_MCASP_PFUNC_AHCLKR_SHIFT     (0x0000001Eu)
#define CSL_MCASP_PFUNC_AHCLKR_RESETVAL  (0x00000000u)

/*----AHCLKR Tokens----*/
#define CSL_MCASP_PFUNC_AHCLKR_MCASP     (0x00000000u)
#define CSL_MCASP_PFUNC_AHCLKR_GPIO      (0x00000001u)

#define CSL_MCASP_PFUNC_ACLKR_MASK       (0x20000000u)
#define CSL_MCASP_PFUNC_ACLKR_SHIFT      (0x0000001Du)
#define CSL_MCASP_PFUNC_ACLKR_RESETVAL   (0x00000000u)

/*----ACLKR Tokens----*/
#define CSL_MCASP_PFUNC_ACLKR_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_ACLKR_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AFSX_MASK        (0x10000000u)
#define CSL_MCASP_PFUNC_AFSX_SHIFT       (0x0000001Cu)
#define CSL_MCASP_PFUNC_AFSX_RESETVAL    (0x00000000u)

/*----AFSX Tokens----*/
#define CSL_MCASP_PFUNC_AFSX_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AFSX_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AHCLKX_MASK      (0x08000000u)
#define CSL_MCASP_PFUNC_AHCLKX_SHIFT     (0x0000001Bu)
#define CSL_MCASP_PFUNC_AHCLKX_RESETVAL  (0x00000000u)

/*----AHCLKX Tokens----*/
#define CSL_MCASP_PFUNC_AHCLKX_MCASP     (0x00000000u)
#define CSL_MCASP_PFUNC_AHCLKX_GPIO      (0x00000001u)

#define CSL_MCASP_PFUNC_ACLKX_MASK       (0x04000000u)
#define CSL_MCASP_PFUNC_ACLKX_SHIFT      (0x0000001Au)
#define CSL_MCASP_PFUNC_ACLKX_RESETVAL   (0x00000000u)

/*----ACLKX Tokens----*/
#define CSL_MCASP_PFUNC_ACLKX_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_ACLKX_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AMUTE_MASK       (0x02000000u)
#define CSL_MCASP_PFUNC_AMUTE_SHIFT      (0x00000019u)
#define CSL_MCASP_PFUNC_AMUTE_RESETVAL   (0x00000000u)

/*----AMUTE Tokens----*/
#define CSL_MCASP_PFUNC_AMUTE_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AMUTE_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR15_MASK       (0x00008000u)
#define CSL_MCASP_PFUNC_AXR15_SHIFT      (0x0000000Fu)
#define CSL_MCASP_PFUNC_AXR15_RESETVAL   (0x00000000u)

/*----AXR15 Tokens----*/
#define CSL_MCASP_PFUNC_AXR15_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR15_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR14_MASK       (0x00004000u)
#define CSL_MCASP_PFUNC_AXR14_SHIFT      (0x0000000Eu)
#define CSL_MCASP_PFUNC_AXR14_RESETVAL   (0x00000000u)

/*----AXR14 Tokens----*/
#define CSL_MCASP_PFUNC_AXR14_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR14_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR13_MASK       (0x00002000u)
#define CSL_MCASP_PFUNC_AXR13_SHIFT      (0x0000000Du)
#define CSL_MCASP_PFUNC_AXR13_RESETVAL   (0x00000000u)

/*----AXR13 Tokens----*/
#define CSL_MCASP_PFUNC_AXR13_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR13_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR12_MASK       (0x00001000u)
#define CSL_MCASP_PFUNC_AXR12_SHIFT      (0x0000000Cu)
#define CSL_MCASP_PFUNC_AXR12_RESETVAL   (0x00000000u)

/*----AXR12 Tokens----*/
#define CSL_MCASP_PFUNC_AXR12_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR12_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR11_MASK       (0x00000800u)
#define CSL_MCASP_PFUNC_AXR11_SHIFT      (0x0000000Bu)
#define CSL_MCASP_PFUNC_AXR11_RESETVAL   (0x00000000u)

/*----AXR11 Tokens----*/
#define CSL_MCASP_PFUNC_AXR11_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR11_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR10_MASK       (0x00000400u)
#define CSL_MCASP_PFUNC_AXR10_SHIFT      (0x0000000Au)
#define CSL_MCASP_PFUNC_AXR10_RESETVAL   (0x00000000u)

/*----AXR10 Tokens----*/
#define CSL_MCASP_PFUNC_AXR10_MCASP      (0x00000000u)
#define CSL_MCASP_PFUNC_AXR10_GPIO       (0x00000001u)

#define CSL_MCASP_PFUNC_AXR9_MASK        (0x00000200u)
#define CSL_MCASP_PFUNC_AXR9_SHIFT       (0x00000009u)
#define CSL_MCASP_PFUNC_AXR9_RESETVAL    (0x00000000u)

/*----AXR9 Tokens----*/
#define CSL_MCASP_PFUNC_AXR9_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR9_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR8_MASK        (0x00000100u)
#define CSL_MCASP_PFUNC_AXR8_SHIFT       (0x00000008u)
#define CSL_MCASP_PFUNC_AXR8_RESETVAL    (0x00000000u)

/*----AXR8 Tokens----*/
#define CSL_MCASP_PFUNC_AXR8_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR8_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR7_MASK        (0x00000080u)
#define CSL_MCASP_PFUNC_AXR7_SHIFT       (0x00000007u)
#define CSL_MCASP_PFUNC_AXR7_RESETVAL    (0x00000000u)

/*----AXR7 Tokens----*/
#define CSL_MCASP_PFUNC_AXR7_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR7_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR6_MASK        (0x00000040u)
#define CSL_MCASP_PFUNC_AXR6_SHIFT       (0x00000006u)
#define CSL_MCASP_PFUNC_AXR6_RESETVAL    (0x00000000u)

/*----AXR6 Tokens----*/
#define CSL_MCASP_PFUNC_AXR6_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR6_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR5_MASK        (0x00000020u)
#define CSL_MCASP_PFUNC_AXR5_SHIFT       (0x00000005u)
#define CSL_MCASP_PFUNC_AXR5_RESETVAL    (0x00000000u)

/*----AXR5 Tokens----*/
#define CSL_MCASP_PFUNC_AXR5_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR5_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR4_MASK        (0x00000010u)
#define CSL_MCASP_PFUNC_AXR4_SHIFT       (0x00000004u)
#define CSL_MCASP_PFUNC_AXR4_RESETVAL    (0x00000000u)

/*----AXR4 Tokens----*/
#define CSL_MCASP_PFUNC_AXR4_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR4_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR3_MASK        (0x00000008u)
#define CSL_MCASP_PFUNC_AXR3_SHIFT       (0x00000003u)
#define CSL_MCASP_PFUNC_AXR3_RESETVAL    (0x00000000u)

/*----AXR3 Tokens----*/
#define CSL_MCASP_PFUNC_AXR3_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR3_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR2_MASK        (0x00000004u)
#define CSL_MCASP_PFUNC_AXR2_SHIFT       (0x00000002u)
#define CSL_MCASP_PFUNC_AXR2_RESETVAL    (0x00000000u)

/*----AXR2 Tokens----*/
#define CSL_MCASP_PFUNC_AXR2_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR2_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR1_MASK        (0x00000002u)
#define CSL_MCASP_PFUNC_AXR1_SHIFT       (0x00000001u)
#define CSL_MCASP_PFUNC_AXR1_RESETVAL    (0x00000000u)

/*----AXR1 Tokens----*/
#define CSL_MCASP_PFUNC_AXR1_MCASP       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR1_GPIO        (0x00000001u)

#define CSL_MCASP_PFUNC_AXR0_MASK        (0x00000001u)
#define CSL_MCASP_PFUNC_AXR0_SHIFT       (0x00000000u)
#define CSL_MCASP_PFUNC_AXR0_RESETVAL    (0x00000000u)