cslr_chip.h

Configuring External Interrupts on TMS320C672x Devices

#define CSL_CHIP_FADCR_L1NAN1_MASK       (0x1u)
#define CSL_CHIP_FADCR_L1NAN1_SHIFT      (0x0u)
#define CSL_CHIP_FADCR_L1NAN1_RESETVAL   (0x0u)

/*----L1NAN1 Tokens----*/
#define CSL_CHIP_FADCR_L1NAN1_SRC1_NONAN (0x0u)
#define CSL_CHIP_FADCR_L1NAN1_SRC1_NAN   (0x1u)

#define CSL_CHIP_FADCR_RESETVAL          (0x0u)

/* FAUCR */

#define CSL_CHIP_FAUCR_S2DIV0_MASK       (0x4000000u)
#define CSL_CHIP_FAUCR_S2DIV0_SHIFT      (0x1Au)
#define CSL_CHIP_FAUCR_S2DIV0_RESETVAL   (0x0u)

/*----S2DIV0 Tokens----*/
#define CSL_CHIP_FAUCR_S2DIV0_ZER0       (0x0u)
#define CSL_CHIP_FAUCR_S2DIV0_NONZERO    (0x1u)

#define CSL_CHIP_FAUCR_S2UNORD_MASK      (0x2000000u)
#define CSL_CHIP_FAUCR_S2UNORD_SHIFT     (0x19u)
#define CSL_CHIP_FAUCR_S2UNORD_RESETVAL  (0x0u)

/*----S2UNORD Tokens----*/
#define CSL_CHIP_FAUCR_S2UNORD_NAN_NOSRC (0x0u)
#define CSL_CHIP_FAUCR_S2UNORD_NAN_SRC   (0x1u)

#define CSL_CHIP_FAUCR_S2UNDER_MASK      (0x1000000u)
#define CSL_CHIP_FAUCR_S2UNDER_SHIFT     (0x18u)
#define CSL_CHIP_FAUCR_S2UNDER_RESETVAL  (0x0u)

/*----S2UNDER Tokens----*/
#define CSL_CHIP_FAUCR_S2UNDER_NO_UDRFLW (0x0u)
#define CSL_CHIP_FAUCR_S2UNDER_UDRFLW    (0x1u)

#define CSL_CHIP_FAUCR_S2INEX_MASK       (0x800000u)
#define CSL_CHIP_FAUCR_S2INEX_SHIFT      (0x17u)
#define CSL_CHIP_FAUCR_S2INEX_RESETVAL   (0x0u)

/*----S2INEX Tokens----*/
#define CSL_CHIP_FAUCR_S2INEX_CLR        (0x0u)
#define CSL_CHIP_FAUCR_S2INEX_SET        (0x1u)

#define CSL_CHIP_FAUCR_S2OVER_MASK       (0x400000u)
#define CSL_CHIP_FAUCR_S2OVER_SHIFT      (0x16u)
#define CSL_CHIP_FAUCR_S2OVER_RESETVAL   (0x0u)

/*----S2OVER Tokens----*/
#define CSL_CHIP_FAUCR_S2OVER_NO_OVRFLW  (0x0u)
#define CSL_CHIP_FAUCR_S2OVER_OVRFLW     (0x1u)

#define CSL_CHIP_FAUCR_S2INFO_MASK       (0x200000u)
#define CSL_CHIP_FAUCR_S2INFO_SHIFT      (0x15u)
#define CSL_CHIP_FAUCR_S2INFO_RESETVAL   (0x0u)

/*----S2INFO Tokens----*/
#define CSL_CHIP_FAUCR_S2INFO_NO_SIGNINF (0x0u)
#define CSL_CHIP_FAUCR_S2INFO_SIGNINF    (0x1u)

#define CSL_CHIP_FAUCR_S2INVAL_MASK      (0x100000u)
#define CSL_CHIP_FAUCR_S2INVAL_SHIFT     (0x14u)
#define CSL_CHIP_FAUCR_S2INVAL_RESETVAL  (0x0u)

/*----S2INVAL Tokens----*/
#define CSL_CHIP_FAUCR_S2INVAL_NAN_NOSRC (0x0u)
#define CSL_CHIP_FAUCR_S2INVAL_NAN_SRC   (0x1u)

#define CSL_CHIP_FAUCR_S2DEN2_MASK       (0x80000u)
#define CSL_CHIP_FAUCR_S2DEN2_SHIFT      (0x13u)
#define CSL_CHIP_FAUCR_S2DEN2_RESETVAL   (0x0u)

/*----S2DEN2 Tokens----*/
#define CSL_CHIP_FAUCR_S2DEN2_SRC2_NODNORM (0x0u)
#define CSL_CHIP_FAUCR_S2DEN2_SRC2_DNORM (0x1u)

#define CSL_CHIP_FAUCR_S2DEN1_MASK       (0x40000u)
#define CSL_CHIP_FAUCR_S2DEN1_SHIFT      (0x12u)
#define CSL_CHIP_FAUCR_S2DEN1_RESETVAL   (0x0u)

/*----S2DEN1 Tokens----*/
#define CSL_CHIP_FAUCR_S2DEN1_SRC1_NODNORM (0x0u)
#define CSL_CHIP_FAUCR_S2DEN1_SRC1_DNORM (0x1u)

#define CSL_CHIP_FAUCR_S2NAN2_MASK       (0x20000u)
#define CSL_CHIP_FAUCR_S2NAN2_SHIFT      (0x11u)
#define CSL_CHIP_FAUCR_S2NAN2_RESETVAL   (0x0u)

/*----S2NAN2 Tokens----*/
#define CSL_CHIP_FAUCR_S2NAN2_SRC2_NONAN (0x0u)
#define CSL_CHIP_FAUCR_S2NAN2_SRC2_NAN   (0x1u)

#define CSL_CHIP_FAUCR_S2NAN1_MASK       (0x10000u)
#define CSL_CHIP_FAUCR_S2NAN1_SHIFT      (0x10u)
#define CSL_CHIP_FAUCR_S2NAN1_RESETVAL   (0x0u)

/*----S2NAN1 Tokens----*/
#define CSL_CHIP_FAUCR_S2NAN1_SRC1_NONAN (0x0u)
#define CSL_CHIP_FAUCR_S2NAN1_SRC1_NAN   (0x1u)

#define CSL_CHIP_FAUCR_S1DIVO_MASK       (0x400u)
#define CSL_CHIP_FAUCR_S1DIVO_SHIFT      (0xAu)
#define CSL_CHIP_FAUCR_S1DIVO_RESETVAL   (0x0u)

/*----S1DIVO Tokens----*/
#define CSL_CHIP_FAUCR_S1DIVO_ZER0       (0x0u)
#define CSL_CHIP_FAUCR_S1DIVO_NONZERO    (0x1u)

#define CSL_CHIP_FAUCR_S1UNORD_MASK      (0x200u)
#define CSL_CHIP_FAUCR_S1UNORD_SHIFT     (0x9u)
#define CSL_CHIP_FAUCR_S1UNORD_RESETVAL  (0x0u)

/*----S1UNORD Tokens----*/
#define CSL_CHIP_FAUCR_S1UNORD_NAN_NOSRC (0x0u)
#define CSL_CHIP_FAUCR_S1UNORD_NAN_SRC   (0x1u)

#define CSL_CHIP_FAUCR_S1UNDER_MASK      (0x100u)
#define CSL_CHIP_FAUCR_S1UNDER_SHIFT     (0x8u)
#define CSL_CHIP_FAUCR_S1UNDER_RESETVAL  (0x0u)

/*----S1UNDER Tokens----*/
#define CSL_CHIP_FAUCR_S1UNDER_NO_UDRFLW (0x0u)
#define CSL_CHIP_FAUCR_S1UNDER_UDRFLW    (0x1u)

#define CSL_CHIP_FAUCR_S1INEX_MASK       (0x80u)
#define CSL_CHIP_FAUCR_S1INEX_SHIFT      (0x7u)
#define CSL_CHIP_FAUCR_S1INEX_RESETVAL   (0x0u)

/*----S1INEX Tokens----*/
#define CSL_CHIP_FAUCR_S1INEX_CLR        (0x0u)
#define CSL_CHIP_FAUCR_S1INEX_SET        (0x1u)

#define CSL_CHIP_FAUCR_S1OVER_MASK       (0x40u)
#define CSL_CHIP_FAUCR_S1OVER_SHIFT      (0x6u)
#define CSL_CHIP_FAUCR_S1OVER_RESETVAL   (0x0u)

/*----S1OVER Tokens----*/
#define CSL_CHIP_FAUCR_S1OVER_NO_OVRFLW  (0x0u)
#define CSL_CHIP_FAUCR_S1OVER_OVRFLW     (0x1u)

#define CSL_CHIP_FAUCR_S1INFO_MASK       (0x20u)
#define CSL_CHIP_FAUCR_S1INFO_SHIFT      (0x5u)
#define CSL_CHIP_FAUCR_S1INFO_RESETVAL   (0x0u)

/*----S1INFO Tokens----*/
#define CSL_CHIP_FAUCR_S1INFO_NO_SIGNINF (0x0u)
#define CSL_CHIP_FAUCR_S1INFO_SIGNINF    (0x1u)

#define CSL_CHIP_FAUCR_S1INVAL_MASK      (0x10u)
#define CSL_CHIP_FAUCR_S1INVAL_SHIFT     (0x4u)
#define CSL_CHIP_FAUCR_S1INVAL_RESETVAL  (0x0u)

/*----S1INVAL Tokens----*/
#define CSL_CHIP_FAUCR_S1INVAL_NAN_NOSRC (0x0u)
#define CSL_CHIP_FAUCR_S1INVAL_NAN_SRC   (0x1u)

#define CSL_CHIP_FAUCR_S1DEN2_MASK       (0x8u)
#define CSL_CHIP_FAUCR_S1DEN2_SHIFT      (0x3u)
#define CSL_CHIP_FAUCR_S1DEN2_RESETVAL   (0x0u)

/*----S1DEN2 Tokens----*/
#define CSL_CHIP_FAUCR_S1DEN2_SRC2_NDNORM (0x0u)
#define CSL_CHIP_FAUCR_S1DEN2_SRC2_DNORM (0x1u)

#define CSL_CHIP_FAUCR_S1DEN1_MASK       (0x4u)
#define CSL_CHIP_FAUCR_S1DEN1_SHIFT      (0x2u)
#define CSL_CHIP_FAUCR_S1DEN1_RESETVAL   (0x0u)

/*----S1DEN1 Tokens----*/
#define CSL_CHIP_FAUCR_S1DEN1_SRC1_NODNORM (0x0u)
#define CSL_CHIP_FAUCR_S1DEN1_SRC1_DNORM (0x1u)

#define CSL_CHIP_FAUCR_S1NAN2_MASK       (0x2u)
#define CSL_CHIP_FAUCR_S1NAN2_SHIFT      (0x1u)
#define CSL_CHIP_FAUCR_S1NAN2_RESETVAL   (0x0u)

/*----S1NAN2 Tokens----*/
#define CSL_CHIP_FAUCR_S1NAN2_SRC2_NONAN (0x0u)
#define CSL_CHIP_FAUCR_S1NAN2_SRC2_NAN   (0x1u)

#define CSL_CHIP_FAUCR_S1NAN1_MASK       (0x1u)
#define CSL_CHIP_FAUCR_S1NAN1_SHIFT      (0x0u)
#define CSL_CHIP_FAUCR_S1NAN1_RESETVAL   (0x0u)

/*----S1NAN1 Tokens----*/
#define CSL_CHIP_FAUCR_S1NAN1_SRC1_NONAN (0x0u)
#define CSL_CHIP_FAUCR_S1NAN1_SRC1_NAN   (0x1u)

#define CSL_CHIP_FAUCR_RESETVAL          (0x0u)

/* FMCR */

#define CSL_CHIP_FMCR_M2RMODE_MASK       (0x6000000u)
#define CSL_CHIP_FMCR_M2RMODE_SHIFT      (0x19u)
#define CSL_CHIP_FMCR_M2RMODE_RESETVAL   (0x0u)

/*----M2RMODE Tokens----*/
#define CSL_CHIP_FMCR_M2RMODE_RTOFP      (0x0u)
#define CSL_CHIP_FMCR_M2RMODE_RTOZERO    (0x1u)
#define CSL_CHIP_FMCR_M2RMODE_RTOINF     (0x2u)
#define CSL_CHIP_FMCR_M2RMODE_RTONEGINF  (0x3u)

#define CSL_CHIP_FMCR_M2UNDER_MASK       (0x1000000u)
#define CSL_CHIP_FMCR_M2UNDER_SHIFT      (0x18u)
#define CSL_CHIP_FMCR_M2UNDER_RESETVAL   (0x0u)

/*----M2UNDER Tokens----*/
#define CSL_CHIP_FMCR_M2UNDER_NO_UDRFLW  (0x0u)
#define CSL_CHIP_FMCR_M2UNDER_UDRFLW     (0x1u)

#define CSL_CHIP_FMCR_M2INEX_MASK        (0x800000u)
#define CSL_CHIP_FMCR_M2INEX_SHIFT       (0x17u)
#define CSL_CHIP_FMCR_M2INEX_RESETVAL    (0x0u)

/*----M2INEX Tokens----*/
#define CSL_CHIP_FMCR_M2INEX_CLR         (0x0u)
#define CSL_CHIP_FMCR_M2INEX_SET         (0x1u)

#define CSL_CHIP_FMCR_M2OVER_MASK        (0x400000u)
#define CSL_CHIP_FMCR_M2OVER_SHIFT       (0x16u)
#define CSL_CHIP_FMCR_M2OVER_RESETVAL    (0x0u)

/*----M2OVER Tokens----*/
#define CSL_CHIP_FMCR_M2OVER_NO_OVRFLW   (0x0u)
#define CSL_CHIP_FMCR_M2OVER_OVRFLW      (0x1u)

#define CSL_CHIP_FMCR_M2INFO_MASK        (0x200000u)
#define CSL_CHIP_FMCR_M2INFO_SHIFT       (0x15u)
#define CSL_CHIP_FMCR_M2INFO_RESETVAL    (0x0u)

/*----M2INFO Tokens----*/
#define CSL_CHIP_FMCR_M2INFO_NO_SIGNINF  (0x0u)
#define CSL_CHIP_FMCR_M2INFO_SIGNINF     (0x1u)

#define CSL_CHIP_FMCR_M2INVAL_MASK       (0x100000u)
#define CSL_CHIP_FMCR_M2INVAL_SHIFT      (0x14u)
#define CSL_CHIP_FMCR_M2INVAL_RESETVAL   (0x0u)

/*----M2INVAL Tokens----*/
#define CSL_CHIP_FMCR_M2INVAL_NAN_NOSRC  (0x0u)
#define CSL_CHIP_FMCR_M2INVAL_NAN_SRC    (0x1u)

#define CSL_CHIP_FMCR_M2DEN2_MASK        (0x80000u)
#define CSL_CHIP_FMCR_M2DEN2_SHIFT       (0x13u)
#define CSL_CHIP_FMCR_M2DEN2_RESETVAL    (0x0u)

/*----M2DEN2 Tokens----*/
#define CSL_CHIP_FMCR_M2DEN2_SRC2_NODNORM (0x0u)
#define CSL_CHIP_FMCR_M2DEN2_SRC2_DNORM  (0x1u)

#define CSL_CHIP_FMCR_M2DEN1_MASK        (0x40000u)
#define CSL_CHIP_FMCR_M2DEN1_SHIFT       (0x12u)
#define CSL_CHIP_FMCR_M2DEN1_RESETVAL    (0x0u)

/*----M2DEN1 Tokens----*/
#define CSL_CHIP_FMCR_M2DEN1_SRC1_NODNORM (0x0u)
#define CSL_CHIP_FMCR_M2DEN1_SRC1_DNORM  (0x1u)

#define CSL_CHIP_FMCR_M2NAN2_MASK        (0x20000u)
#define CSL_CHIP_FMCR_M2NAN2_SHIFT       (0x11u)
#define CSL_CHIP_FMCR_M2NAN2_RESETVAL    (0x0u)

/*----M2NAN2 Tokens----*/
#define CSL_CHIP_FMCR_M2NAN2_SRC2_NONAN  (0x0u)
#define CSL_CHIP_FMCR_M2NAN2_SRC2_NAN    (0x1u)

#define CSL_CHIP_FMCR_M2NAN1_MASK        (0x10000u)
#define CSL_CHIP_FMCR_M2NAN1_SHIFT       (0x10u)
#define CSL_CHIP_FMCR_M2NAN1_RESETVAL    (0x0u)

/*----M2NAN1 Tokens----*/
#define CSL_CHIP_FMCR_M2NAN1_SRC1_NONAN  (0x0u)
#define CSL_CHIP_FMCR_M2NAN1_SRC1_NAN    (0x1u)

#define CSL_CHIP_FMCR_M1RMODE_MASK       (0x600u)
#define CSL_CHIP_FMCR_M1RMODE_SHIFT      (0x9u)
#define CSL_CHIP_FMCR_M1RMODE_RESETVAL   (0x0u)

/*----M1RMODE Tokens----*/
#define CSL_CHIP_FMCR_M1RMODE_RTOFP      (0x0u)
#define CSL_CHIP_FMCR_M1RMODE_RTOZERO    (0x1u)
#define CSL_CHIP_FMCR_M1RMODE_RTOINF     (0x2u)
#define CSL_CHIP_FMCR_M1RMODE_RTONEGINF  (0x3u)

#define CSL_CHIP_FMCR_M1UNDER_MASK       (0x100u)
#define CSL_CHIP_FMCR_M1UNDER_SHIFT      (0x8u)
#define CSL_CHIP_FMCR_M1UNDER_RESETVAL   (0x0u)

/*----M1UNDER Tokens----*/
#define CSL_CHIP_FMCR_M1UNDER_NO_UDRFLW  (0x0u)
#define CSL_CHIP_FMCR_M1UNDER_UDRFLW     (0x1u)

#define CSL_CHIP_FMCR_M1INEX_MASK        (0x80u)
#define CSL_CHIP_FMCR_M1INEX_SHIFT       (0x7u)
#define CSL_CHIP_FMCR_M1INEX_RESETVAL    (0x0u)

/*----M1INEX Tokens----*/
#define CSL_CHIP_FMCR_M1INEX_CLR         (0x0u)
#define CSL_CHIP_FMCR_M1INEX_SET         (0x1u)

#define CSL_CHIP_FMCR_M1OVER_MASK        (0x40u)
#define CSL_CHIP_FMCR_M1OVER_SHIFT       (0x6u)
#define CSL_CHIP_FMCR_M1OVER_RESETVAL    (0x0u)

/*----M1OVER Tokens----*/
#define CSL_CHIP_FMCR_M1OVER_NO_OVRFLW   (0x0u)
#define CSL_CHIP_FMCR_M1OVER_OVRFLW      (0x1u)

#define CSL_CHIP_FMCR_M1INFO_MASK        (0x20u)
#define CSL_CHIP_FMCR_M1INFO_SHIFT       (0x5u)
#define CSL_CHIP_FMCR_M1INFO_RESETVAL    (0x0u)

/*----M1INFO Tokens----*/
#define CSL_CHIP_FMCR_M1INFO_NO_SIGNINF  (0x0u)
#define CSL_CHIP_FMCR_M1INFO_SIGNINF     (0x1u)

#define CSL_CHIP_FMCR_M1INVAL_MASK       (0x10u)
#define CSL_CHIP_FMCR_M1INVAL_SHIFT      (0x4u)
#define CSL_CHIP_FMCR_M1INVAL_RESETVAL   (0x0u)

/*----M1INVAL Tokens----*/
#define CSL_CHIP_FMCR_M1INVAL_NAN_NOSRC  (0x0u)
#define CSL_CHIP_FMCR_M1INVAL_NAN_SRC    (0x1u)

#define CSL_CHIP_FMCR_M1DEN2_MASK        (0x8u)
#define CSL_CHIP_FMCR_M1DEN2_SHIFT       (0x3u)
#define CSL_CHIP_FMCR_M1DEN2_RESETVAL    (0x0u)

/*----M1DEN2 Tokens----*/
#define CSL_CHIP_FMCR_M1DEN2_SRC2_NODNORM (0x0u)
#define CSL_CHIP_FMCR_M1DEN2_SRC2_DNORM  (0x1u)

#define CSL_CHIP_FMCR_M1DEN1_MASK        (0x4u)
#define CSL_CHIP_FMCR_M1DEN1_SHIFT       (0x2u)
#define CSL_CHIP_FMCR_M1DEN1_RESETVAL    (0x0u)

/*----M1DEN1 Tokens----*/
#define CSL_CHIP_FMCR_M1DEN1_SRC1_NODNORM (0x0u)
#define CSL_CHIP_FMCR_M1DEN1_SRC1_DNORM  (0x1u)

#define CSL_CHIP_FMCR_M1NAN2_MASK        (0x2u)
#define CSL_CHIP_FMCR_M1NAN2_SHIFT       (0x1u)
#define CSL_CHIP_FMCR_M1NAN2_RESETVAL    (0x0u)

/*----M1NAN2 Tokens----*/
#define CSL_CHIP_FMCR_M1NAN2_SRC2_NONAN  (0x0u)
#define CSL_CHIP_FMCR_M1NAN2_SRC2_NAN    (0x1u)

#define CSL_CHIP_FMCR_M1NAN1_MASK        (0x1u)
#define CSL_CHIP_FMCR_M1NAN1_SHIFT       (0x0u)
#define CSL_CHIP_FMCR_M1NAN1_RESETVAL    (0x0u)

/*----M1NAN1 Tokens----*/
#define CSL_CHIP_FMCR_M1NAN1_SRC1_NONAN  (0x0u)
#define CSL_CHIP_FMCR_M1NAN1_SRC1_NAN    (0x1u)

#define CSL_CHIP_FMCR_RESETVAL           (0x0u)

#endif