📄 cslr_chip.h
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/*********************************************************************
* Copyright (C) 2003-2005 Texas Instruments Incorporated.
* All Rights Reserved
*********************************************************************/
/** @file cslr_chip.h
*
* \brief This file contains the Register Desciptions for CHIP
*
*********************************************************************/
#ifndef _CSLR_CHIP_H_
#define _CSLR_CHIP_H_
#include <cslr.h>
#include <csl_types.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
/**
* Register Overlay structure for memory mapped chip registers
*/
typedef struct {
/** CFGPIN0 */
volatile Uint32 CFGPIN0;
/** CFGPIN1 */
volatile Uint32 CFGPIN1;
/** CFGHPI */
volatile Uint32 CFGHPI;
/** CFGHPIAMSB */
volatile Uint32 CFGHPIAMSB;
/** CFGHPIAUMB */
volatile Uint32 CFGHPIAUMB;
/** CFGRTI */
volatile Uint32 CFGRTI;
/** CGFMCASP0 */
volatile Uint32 CFGMCASP0;
/** CGFMCASP1 */
volatile Uint32 CFGMCASP1;
/** CGFMCASP2 */
volatile Uint32 CFGMCASP2;
/** CGFBRIDGE */
volatile Uint32 CFGBRIDGE;
volatile Uint8 RSVD0[88];
/** IDREG */
volatile Uint32 IDREG;
} CSL_ChipRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* CFGPIN0 */
#define CSL_CHIP_CFGPIN0_PINCAP7_MASK (0x00000080u)
#define CSL_CHIP_CFGPIN0_PINCAP7_SHIFT (0x00000007u)
#define CSL_CHIP_CFGPIN0_PINCAP7_RESETVAL (0x00000000u)
/*----PINCAP7 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP7_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP7_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP6_MASK (0x00000040u)
#define CSL_CHIP_CFGPIN0_PINCAP6_SHIFT (0x00000006u)
#define CSL_CHIP_CFGPIN0_PINCAP6_RESETVAL (0x00000000u)
/*----PINCAP6 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP6_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP6_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP5_MASK (0x00000020u)
#define CSL_CHIP_CFGPIN0_PINCAP5_SHIFT (0x00000005u)
#define CSL_CHIP_CFGPIN0_PINCAP5_RESETVAL (0x00000000u)
/*----PINCAP5 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP5_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP5_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP4_MASK (0x00000010u)
#define CSL_CHIP_CFGPIN0_PINCAP4_SHIFT (0x00000004u)
#define CSL_CHIP_CFGPIN0_PINCAP4_RESETVAL (0x00000000u)
/*----PINCAP4 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP4_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP4_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP3_MASK (0x00000008u)
#define CSL_CHIP_CFGPIN0_PINCAP3_SHIFT (0x00000003u)
#define CSL_CHIP_CFGPIN0_PINCAP3_RESETVAL (0x00000000u)
/*----PINCAP3 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP3_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP3_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP2_MASK (0x00000004u)
#define CSL_CHIP_CFGPIN0_PINCAP2_SHIFT (0x00000002u)
#define CSL_CHIP_CFGPIN0_PINCAP2_RESETVAL (0x00000000u)
/*----PINCAP2 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP2_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP2_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP1_MASK (0x00000002u)
#define CSL_CHIP_CFGPIN0_PINCAP1_SHIFT (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP1_RESETVAL (0x00000000u)
/*----PINCAP1 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP1_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP1_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP0_MASK (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP0_SHIFT (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP0_RESETVAL (0x00000000u)
/*----PINCAP0 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP0_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP0_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_RESETVAL (0x00000000u)
/* CFGPIN1 */
#define CSL_CHIP_CFGPIN1_PINCAP15_MASK (0x00000080u)
#define CSL_CHIP_CFGPIN1_PINCAP15_SHIFT (0x00000007u)
#define CSL_CHIP_CFGPIN1_PINCAP15_RESETVAL (0x00000000u)
/*----PINCAP15 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP15_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP15_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP14_MASK (0x00000040u)
#define CSL_CHIP_CFGPIN1_PINCAP14_SHIFT (0x00000006u)
#define CSL_CHIP_CFGPIN1_PINCAP14_RESETVAL (0x00000000u)
/*----PINCAP14 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP14_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP14_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP13_MASK (0x00000020u)
#define CSL_CHIP_CFGPIN1_PINCAP13_SHIFT (0x00000005u)
#define CSL_CHIP_CFGPIN1_PINCAP13_RESETVAL (0x00000000u)
/*----PINCAP13 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP13_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP13_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP12_MASK (0x00000010u)
#define CSL_CHIP_CFGPIN1_PINCAP12_SHIFT (0x00000004u)
#define CSL_CHIP_CFGPIN1_PINCAP12_RESETVAL (0x00000000u)
/*----PINCAP12 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP12_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP12_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP11_MASK (0x00000008u)
#define CSL_CHIP_CFGPIN1_PINCAP11_SHIFT (0x00000003u)
#define CSL_CHIP_CFGPIN1_PINCAP11_RESETVAL (0x00000000u)
/*----PINCAP11 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP11_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP11_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP10_MASK (0x00000004u)
#define CSL_CHIP_CFGPIN1_PINCAP10_SHIFT (0x00000002u)
#define CSL_CHIP_CFGPIN1_PINCAP10_RESETVAL (0x00000000u)
/*----PINCAP10 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP10_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP10_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP9_MASK (0x00000002u)
#define CSL_CHIP_CFGPIN1_PINCAP9_SHIFT (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP9_RESETVAL (0x00000000u)
/*----PINCAP9 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP9_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP9_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP8_MASK (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP8_SHIFT (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP8_RESETVAL (0x00000000u)
/*----PINCAP8 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP8_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP8_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_RESETVAL (0x00000000u)
/* CFGHPI */
#define CSL_CHIP_CFGHPI_BYTEAD_MASK (0x00000010u)
#define CSL_CHIP_CFGHPI_BYTEAD_SHIFT (0x00000004u)
#define CSL_CHIP_CFGHPI_BYTEAD_RESETVAL (0x00000000u)
/*----BYTEAD Tokens----*/
#define CSL_CHIP_CFGHPI_BYTEAD_WADDR (0x00000000u)
#define CSL_CHIP_CFGHPI_BYTEAD_BADDR (0x00000001u)
#define CSL_CHIP_CFGHPI_FULL_MASK (0x00000008u)
#define CSL_CHIP_CFGHPI_FULL_SHIFT (0x00000003u)
#define CSL_CHIP_CFGHPI_FULL_RESETVAL (0x00000000u)
/*----FULL Tokens----*/
#define CSL_CHIP_CFGHPI_FULL_HALF (0x00000000u)
#define CSL_CHIP_CFGHPI_FULL_FULL (0x00000001u)
#define CSL_CHIP_CFGHPI_NMUX_MASK (0x00000004u)
#define CSL_CHIP_CFGHPI_NMUX_SHIFT (0x00000002u)
#define CSL_CHIP_CFGHPI_NMUX_RESETVAL (0x00000000u)
/*----NMUX Tokens----*/
#define CSL_CHIP_CFGHPI_NMUX_DISABLE (0x00000000u)
#define CSL_CHIP_CFGHPI_NMUX_ENABLE (0x00000001u)
#define CSL_CHIP_CFGHPI_PAGEM_MASK (0x00000002u)
#define CSL_CHIP_CFGHPI_PAGEM_SHIFT (0x00000001u)
#define CSL_CHIP_CFGHPI_PAGEM_RESETVAL (0x00000000u)
/*----PAGEM Tokens----*/
#define CSL_CHIP_CFGHPI_PAGEM_VBUS_NOT_OVRRIDE (0x00000000u)
#define CSL_CHIP_CFGHPI_PAGEM_VBUS_OVRRIDE (0x00000001u)
#define CSL_CHIP_CFGHPI_ENA_MASK (0x00000001u)
#define CSL_CHIP_CFGHPI_ENA_SHIFT (0x00000000u)
#define CSL_CHIP_CFGHPI_ENA_RESETVAL (0x00000000u)
/*----ENA Tokens----*/
#define CSL_CHIP_CFGHPI_ENA_HPIENA_CLR (0x00000000u)
#define CSL_CHIP_CFGHPI_ENA_HPIENA_SET (0x00000001u)
#define CSL_CHIP_CFGHPI_RESETVAL (0x00000000u)
/* CFGHPIAMSB */
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_MASK (0x000000FFu)
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_SHIFT (0x00000000u)
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_RESETVAL (0x00000000u)
#define CSL_CHIP_CFGHPIAMSB_RESETVAL (0x00000000u)
/* CFGHPIAUMB */
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_MASK (0x000000FFu)
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_SHIFT (0x00000000u)
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_RESETVAL (0x00000000u)
#define CSL_CHIP_CFGHPIAUMB_RESETVAL (0x00000000u)
/* CFGRTI */
#define CSL_CHIP_CFGRTI_CAPSEL1_MASK (0x00000070u)
#define CSL_CHIP_CFGRTI_CAPSEL1_SHIFT (0x00000004u)
#define CSL_CHIP_CFGRTI_CAPSEL1_RESETVAL (0x00000000u)
/*----CAPSEL1 Tokens----*/
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP0_TX_DMA_RQ (0x00000000u)
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP0_RX_DMA_RQ (0x00000001u)
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP1_TX_DMA_RQ (0x00000002u)
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP1_RX_DMA_RQ (0x00000003u)
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP2_TX_DMA_RQ (0x00000004u)
#define CSL_CHIP_CFGRTI_CAPSEL1_MCASP2_RX_DMA_RQ (0x00000005u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MASK (0x00000007u)
#define CSL_CHIP_CFGRTI_CAPSEL0_SHIFT (0x00000000u)
#define CSL_CHIP_CFGRTI_CAPSEL0_RESETVAL (0x00000000u)
/*----CAPSEL0 Tokens----*/
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP0_TX_DMA_RQ (0x00000000u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP0_RX_DMA_RQ (0x00000001u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP1_TX_DMA_RQ (0x00000002u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP1_RX_DMA_RQ (0x00000003u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP2_TX_DMA_RQ (0x00000004u)
#define CSL_CHIP_CFGRTI_CAPSEL0_MCASP2_RX_DMA_RQ (0x00000005u)
#define CSL_CHIP_CFGRTI_RESETVAL (0x00000000u)
/* CFGMCASP0 */
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_MASK (0x00000007u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_SHIFT (0x00000000u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_RESETVAL (0x00000000u)
/*----AMUTEIN0 Tokens----*/
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_ZERO (0x00000000u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_AXR0_7 (0x00000001u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_AXR0_8_AXR1_5 (0x00000002u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_AXR0_9_AXR1_4 (0x00000003u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_AHCLKR2 (0x00000004u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_SPI0SIMO (0x00000005u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_SPI0SCS_SCL1 (0x00000006u)
#define CSL_CHIP_CFGMCASP0_AMUTEIN0_SPI0ENA_SDA1 (0x00000007u)
#define CSL_CHIP_CFGMCASP0_RESETVAL (0x00000000u)
/* CFGMCASP1 */
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_MASK (0x00000007u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_SHIFT (0x00000000u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_RESETVAL (0x00000000u)
/*----AMUTEIN1 Tokens----*/
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_ZERO (0x00000000u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_AXR0_7 (0x00000001u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_AXR0_8_AXR1_5 (0x00000002u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_AXR0_9_AXR1_4 (0x00000003u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_AHCLKR2 (0x00000004u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_SPI0SIMO (0x00000005u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_SPI0SCS_SCL1 (0x00000006u)
#define CSL_CHIP_CFGMCASP1_AMUTEIN1_SPI0ENA_SDA1 (0x00000007u)
#define CSL_CHIP_CFGMCASP1_RESETVAL (0x00000000u)
/* CFGMCASP2 */
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_MASK (0x00000007u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_SHIFT (0x00000000u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_RESETVAL (0x00000000u)
/*----AMUTEIN2 Tokens----*/
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_ZERO (0x00000000u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_AXR0_7 (0x00000001u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_AXR0_8_AXR1_5 (0x00000002u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_AXR0_9_AXR1_4 (0x00000003u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_AHCLKR2 (0x00000004u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_SPI0SIMO (0x00000005u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_SPI0SCS_SCL1 (0x00000006u)
#define CSL_CHIP_CFGMCASP2_AMUTEIN2_SPI0ENA_SDA1 (0x00000007u)
#define CSL_CHIP_CFGMCASP2_RESETVAL (0x00000000u)
/* CFGBRIDGE */
#define CSL_CHIP_CFGBRIDGE_CSPRST_MASK (0x00000001u)
#define CSL_CHIP_CFGBRIDGE_CSPRST_SHIFT (0x00000000u)
#define CSL_CHIP_CFGBRIDGE_CSPRST_RESETVAL (0x00000001u)
/*----CSPRST Tokens----*/
#define CSL_CHIP_CFGBRIDGE_CSPRST_DISABLE (0x00000000u)
#define CSL_CHIP_CFGBRIDGE_CSPRST_ENABLE (0x00000001u)
#define CSL_CHIP_CFGBRIDGE_RESETVAL (0x00000001u)
/* IDREG */
#define CSL_CHIP_IDREG_REVISION_MASK (0xF0000000u)
#define CSL_CHIP_IDREG_REVISION_SHIFT (0x0000001Cu)
#define CSL_CHIP_IDREG_REVISION_RESETVAL (0x00000000u)
#define CSL_CHIP_IDREG_ID_MASK (0x0FFFFFFFu)
#define CSL_CHIP_IDREG_ID_SHIFT (0x00000000u)
#define CSL_CHIP_IDREG_ID_RESETVAL (0x0B6AB02Fu)
#define CSL_CHIP_IDREG_RESETVAL (0x0B6AB02Fu)
/* AMR */
#define CSL_CHIP_AMR_BK1_MASK (0x3E00000u)
#define CSL_CHIP_AMR_BK1_SHIFT (0x15u)
#define CSL_CHIP_AMR_BK1_RESETVAL (0x0u)
/*----BK1 Tokens----*/
#define CSL_CHIP_AMR_BK1_2 (0x0u)
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