cslr_emif.h

Configuring External Interrupts on TMS320C672x Devices

#define CSL_EMIF_SDTIMR_RESETVAL         (0x0021CF00u)

/* SDSRETR */

#define CSL_EMIF_SDSRETR_T_XS_MASK       (0x0000001Fu)
#define CSL_EMIF_SDSRETR_T_XS_SHIFT      (0x00000000u)
#define CSL_EMIF_SDSRETR_T_XS_RESETVAL   (0x00000019u)

#define CSL_EMIF_SDSRETR_RESETVAL        (0x00000019u)

/* EIRR */

#define CSL_EMIF_EIRR_WR_MASK            (0x00000004u)
#define CSL_EMIF_EIRR_WR_SHIFT           (0x00000002u)
#define CSL_EMIF_EIRR_WR_RESETVAL        (0x00000000u)

/*----WR Tokens----*/
#define CSL_EMIF_EIRR_WR_NOT_OCCURED     (0x00000000u)
#define CSL_EMIF_EIRR_WR_OCCURED         (0x00000001u)

#define CSL_EMIF_EIRR_AT_MASK            (0x00000001u)
#define CSL_EMIF_EIRR_AT_SHIFT           (0x00000000u)
#define CSL_EMIF_EIRR_AT_RESETVAL        (0x00000000u)

/*----AT Tokens----*/
#define CSL_EMIF_EIRR_AT_NOT_OCCURED     (0x00000000u)
#define CSL_EMIF_EIRR_AT_OCCURED         (0x00000001u)

#define CSL_EMIF_EIRR_RESETVAL           (0x00000000u)

/* EIMR */

#define CSL_EMIF_EIMR_WRM_MASK           (0x00000004u)
#define CSL_EMIF_EIMR_WRM_SHIFT          (0x00000002u)
#define CSL_EMIF_EIMR_WRM_RESETVAL       (0x00000000u)

/*----WRM Tokens----*/
#define CSL_EMIF_EIMR_WRM_NOT_OCCURED    (0x00000000u)
#define CSL_EMIF_EIMR_WRM_OCCURED        (0x00000001u)

#define CSL_EMIF_EIMR_ATM_MASK           (0x00000001u)
#define CSL_EMIF_EIMR_ATM_SHIFT          (0x00000000u)
#define CSL_EMIF_EIMR_ATM_RESETVAL       (0x00000000u)

/*----ATM Tokens----*/
#define CSL_EMIF_EIMR_ATM_NOT_OCCURED    (0x00000000u)
#define CSL_EMIF_EIMR_ATM_OCCURED        (0x00000001u)

#define CSL_EMIF_EIMR_RESETVAL           (0x00000000u)

/* EIMSR */

#define CSL_EMIF_EIMSR_WRMSET_MASK       (0x00000004u)
#define CSL_EMIF_EIMSR_WRMSET_SHIFT      (0x00000002u)
#define CSL_EMIF_EIMSR_WRMSET_RESETVAL   (0x00000000u)

/*----WRMSET Tokens----*/
#define CSL_EMIF_EIMSR_WRMSET_ENABLE     (0x00000001u)
#define CSL_EMIF_EIMSR_WRMSET_DISABLE    (0x00000000u)

#define CSL_EMIF_EIMSR_ATMSET_MASK       (0x00000001u)
#define CSL_EMIF_EIMSR_ATMSET_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMSR_ATMSET_RESETVAL   (0x00000000u)

/*----ATMSET Tokens----*/
#define CSL_EMIF_EIMSR_ATMSET_DISABLE    (0x00000000u)
#define CSL_EMIF_EIMSR_ATMSET_ENABLE     (0x00000001u)

#define CSL_EMIF_EIMSR_RESETVAL          (0x00000000u)

/* EIMCR */

#define CSL_EMIF_EIMCR_WRMCLEAR_MASK     (0x00000004u)
#define CSL_EMIF_EIMCR_WRMCLEAR_SHIFT    (0x00000002u)
#define CSL_EMIF_EIMCR_WRMCLEAR_RESETVAL (0x00000000u)

#define CSL_EMIF_EIMCR_ATMCLR_MASK       (0x00000001u)
#define CSL_EMIF_EIMCR_ATMCLR_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMCR_ATMCLR_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMCR_RESETVAL          (0x00000000u)

/* NANDFCR */

#define CSL_EMIF_NANDFCR_CS2ECC_MASK     (0x00000100u)
#define CSL_EMIF_NANDFCR_CS2ECC_SHIFT    (0x00000008u)
#define CSL_EMIF_NANDFCR_CS2ECC_RESETVAL (0x00000000u)

/*----CS2ECC Tokens----*/
#define CSL_EMIF_NANDFCR_CS2ECC_ENABLE   (0x00000001u)
#define CSL_EMIF_NANDFCR_CS2ECC_DISABLE  (0x00000000u)

#define CSL_EMIF_NANDFCR_CS2NAND_MASK    (0x00000001u)
#define CSL_EMIF_NANDFCR_CS2NAND_SHIFT   (0x00000000u)
#define CSL_EMIF_NANDFCR_CS2NAND_RESETVAL (0x00000000u)

/*----CS2NAND Tokens----*/
#define CSL_EMIF_NANDFCR_CS2NAND_ENABLE  (0x00000001u)
#define CSL_EMIF_NANDFCR_CS2NAND_DISABLE (0x00000000u)

#define CSL_EMIF_NANDFCR_RESETVAL        (0x00000000u)

/* NANDFSR */

#define CSL_EMIF_NANDFSR_WAITST_MASK     (0x00000001u)
#define CSL_EMIF_NANDFSR_WAITST_SHIFT    (0x00000000u)
#define CSL_EMIF_NANDFSR_WAITST_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFSR_RESETVAL        (0x00000000u)

/* NANDF1ECC */

#define CSL_EMIF_NANDF1ECC_P2048O_MASK   (0x08000000u)
#define CSL_EMIF_NANDF1ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_EMIF_NANDF1ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1024O_MASK   (0x04000000u)
#define CSL_EMIF_NANDF1ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_EMIF_NANDF1ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P512O_MASK    (0x02000000u)
#define CSL_EMIF_NANDF1ECC_P512O_SHIFT   (0x00000019u)
#define CSL_EMIF_NANDF1ECC_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P256O_MASK    (0x01000000u)
#define CSL_EMIF_NANDF1ECC_P256O_SHIFT   (0x00000018u)
#define CSL_EMIF_NANDF1ECC_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P128O_MASK    (0x00800000u)
#define CSL_EMIF_NANDF1ECC_P128O_SHIFT   (0x00000017u)
#define CSL_EMIF_NANDF1ECC_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P64O_MASK     (0x00400000u)
#define CSL_EMIF_NANDF1ECC_P64O_SHIFT    (0x00000016u)
#define CSL_EMIF_NANDF1ECC_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P32O_MASK     (0x00200000u)
#define CSL_EMIF_NANDF1ECC_P32O_SHIFT    (0x00000015u)
#define CSL_EMIF_NANDF1ECC_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P16O_MASK     (0x00100000u)
#define CSL_EMIF_NANDF1ECC_P16O_SHIFT    (0x00000014u)
#define CSL_EMIF_NANDF1ECC_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P8O_MASK      (0x00080000u)
#define CSL_EMIF_NANDF1ECC_P8O_SHIFT     (0x00000013u)
#define CSL_EMIF_NANDF1ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P4O_MASK      (0x00040000u)
#define CSL_EMIF_NANDF1ECC_P4O_SHIFT     (0x00000012u)
#define CSL_EMIF_NANDF1ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P2O_MASK      (0x00020000u)
#define CSL_EMIF_NANDF1ECC_P2O_SHIFT     (0x00000011u)
#define CSL_EMIF_NANDF1ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1O_MASK      (0x00010000u)
#define CSL_EMIF_NANDF1ECC_P1O_SHIFT     (0x00000010u)
#define CSL_EMIF_NANDF1ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P2048E_MASK   (0x00000800u)
#define CSL_EMIF_NANDF1ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_EMIF_NANDF1ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1024E_MASK   (0x00000400u)
#define CSL_EMIF_NANDF1ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_EMIF_NANDF1ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P512E_MASK    (0x00000200u)
#define CSL_EMIF_NANDF1ECC_P512E_SHIFT   (0x00000009u)
#define CSL_EMIF_NANDF1ECC_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P256E_MASK    (0x00000100u)
#define CSL_EMIF_NANDF1ECC_P256E_SHIFT   (0x00000008u)
#define CSL_EMIF_NANDF1ECC_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P128E_MASK    (0x00000080u)
#define CSL_EMIF_NANDF1ECC_P128E_SHIFT   (0x00000007u)
#define CSL_EMIF_NANDF1ECC_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P64E_MASK     (0x00000040u)
#define CSL_EMIF_NANDF1ECC_P64E_SHIFT    (0x00000006u)
#define CSL_EMIF_NANDF1ECC_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P32E_MASK     (0x00000020u)
#define CSL_EMIF_NANDF1ECC_P32E_SHIFT    (0x00000005u)
#define CSL_EMIF_NANDF1ECC_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P16E_MASK     (0x00000010u)
#define CSL_EMIF_NANDF1ECC_P16E_SHIFT    (0x00000004u)
#define CSL_EMIF_NANDF1ECC_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P8E_MASK      (0x00000008u)
#define CSL_EMIF_NANDF1ECC_P8E_SHIFT     (0x00000003u)
#define CSL_EMIF_NANDF1ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P4E_MASK      (0x00000004u)
#define CSL_EMIF_NANDF1ECC_P4E_SHIFT     (0x00000002u)
#define CSL_EMIF_NANDF1ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P2E_MASK      (0x00000002u)
#define CSL_EMIF_NANDF1ECC_P2E_SHIFT     (0x00000001u)
#define CSL_EMIF_NANDF1ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1E_MASK      (0x00000001u)
#define CSL_EMIF_NANDF1ECC_P1E_SHIFT     (0x00000000u)
#define CSL_EMIF_NANDF1ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_RESETVAL      (0x00000000u)

#endif