cslr_emif.h

Configuring External Interrupts on TMS320C672x Devices

#ifndef _CSLR_EMIF_H_
#define _CSLR_EMIF_H_
/*********************************************************************
 * Copyright (C) 2003-2006 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_emif.h
 * 
 * \brief This file contains the Register Desciptions for EMIF
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 RSVD0[1];
    volatile Uint32 AWCCR;
    volatile Uint32 SDCR;
    volatile Uint32 SDRCR;
    volatile Uint32 A1CR;
    volatile Uint32 RSVD1[3];
    volatile Uint32 SDTIMR;
    volatile Uint32 RSVD2[6];
    volatile Uint32 SDSRETR;
    volatile Uint32 EIRR;
    volatile Uint32 EIMR;
    volatile Uint32 EIMSR;
    volatile Uint32 EIMCR;
    volatile Uint32 RSVD3[4];
    volatile Uint32 NANDFCR;
    volatile Uint32 NANDFSR;
    volatile Uint32 RSVD4[2];
    volatile Uint32 NANDF1ECC;
} CSL_EmifRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* AWCCR */

#define CSL_EMIF_AWCCR_WP0_MASK          (0x10000000u)
#define CSL_EMIF_AWCCR_WP0_SHIFT         (0x0000001Cu)
#define CSL_EMIF_AWCCR_WP0_RESETVAL      (0x00000001u)

/*----WP0 Tokens----*/
#define CSL_EMIF_AWCCR_WP0_LOW           (0x00000000u)
#define CSL_EMIF_AWCCR_WP0_HIGHI         (0x00000001u)

#define CSL_EMIF_AWCCR_MEWC_MASK         (0x000000FFu)
#define CSL_EMIF_AWCCR_MEWC_SHIFT        (0x00000000u)
#define CSL_EMIF_AWCCR_MEWC_RESETVAL     (0x00000080u)

#define CSL_EMIF_AWCCR_RESETVAL          (0x10000080u)

/* SDCR */

#define CSL_EMIF_SDCR_SR_MASK            (0x80000000u)
#define CSL_EMIF_SDCR_SR_SHIFT           (0x0000001Fu)
#define CSL_EMIF_SDCR_SR_RESETVAL        (0x00000000u)

/*----SR Tokens----*/
#define CSL_EMIF_SDCR_SR_DISABLE         (0x00000000u)
#define CSL_EMIF_SDCR_SR_ENABLE          (0x00000001u)

#define CSL_EMIF_SDCR_NM_MASK            (0x00004000u)
#define CSL_EMIF_SDCR_NM_SHIFT           (0x0000000Eu)
#define CSL_EMIF_SDCR_NM_RESETVAL        (0x00000000u)

/*----NM Tokens----*/
#define CSL_EMIF_SDCR_NM_32BIT_DATA      (0x00000000u)
#define CSL_EMIF_SDCR_NM_16BIT_DATA      (0x00000001u)

#define CSL_EMIF_SDCR_CL_MASK            (0x00000E00u)
#define CSL_EMIF_SDCR_CL_SHIFT           (0x00000009u)
#define CSL_EMIF_SDCR_CL_RESETVAL        (0x00000003u)

/*----CL Tokens----*/
#define CSL_EMIF_SDCR_CL_LATENCY_2       (0x00000002u)
#define CSL_EMIF_SDCR_CL_LATENCY_3       (0x00000003u)

#define CSL_EMIF_SDCR_BIT11_9LOCK_MASK   (0x00000100u)
#define CSL_EMIF_SDCR_BIT11_9LOCK_SHIFT  (0x00000008u)
#define CSL_EMIF_SDCR_BIT11_9LOCK_RESETVAL (0x00000000u)

/*----BIT11_9LOCK Tokens----*/
#define CSL_EMIF_SDCR_BIT11_9LOCK_UNLOCK (0x00000001u)

#define CSL_EMIF_SDCR_IBANK_MASK         (0x00000070u)
#define CSL_EMIF_SDCR_IBANK_SHIFT        (0x00000004u)
#define CSL_EMIF_SDCR_IBANK_RESETVAL     (0x00000002u)

/*----IBANK Tokens----*/
#define CSL_EMIF_SDCR_IBANK_NO_OF_BANK_1 (0x00000000u)
#define CSL_EMIF_SDCR_IBANK_NO_OF_BANK_2 (0x00000001u)
#define CSL_EMIF_SDCR_IBANK_NO_OF_BANK_4 (0x00000002u)

#define CSL_EMIF_SDCR_PAGESIZE_MASK      (0x00000007u)
#define CSL_EMIF_SDCR_PAGESIZE_SHIFT     (0x00000000u)
#define CSL_EMIF_SDCR_PAGESIZE_RESETVAL  (0x00000000u)

/*----PAGESIZE Tokens----*/
#define CSL_EMIF_SDCR_PAGESIZE_256WORD_8COL_ADDR (0x00000000u)
#define CSL_EMIF_SDCR_PAGESIZE_512WORD_9COL_ADDR (0x00000001u)
#define CSL_EMIF_SDCR_PAGESIZE_1024WORD_10COL_ADDR (0x00000002u)
#define CSL_EMIF_SDCR_PAGESIZE_2048WORD_11COL_ADDR (0x00000003u)

#define CSL_EMIF_SDCR_RESETVAL           (0x00000620u)

/* SDRCR */

#define CSL_EMIF_SDRCR_RR_MASK           (0x00001FFFu)
#define CSL_EMIF_SDRCR_RR_SHIFT          (0x00000000u)
#define CSL_EMIF_SDRCR_RR_RESETVAL       (0x00000190u)

/*----RR Tokens----*/
#define CSL_EMIF_SDRCR_RR_DEFAULT        (0x00000190u)

#define CSL_EMIF_SDRCR_RESETVAL          (0x00000190u)

/* A1CR */

#define CSL_EMIF_A1CR_SS_MASK            (0x80000000u)
#define CSL_EMIF_A1CR_SS_SHIFT           (0x0000001Fu)
#define CSL_EMIF_A1CR_SS_RESETVAL        (0x00000000u)

/*----SS Tokens----*/
#define CSL_EMIF_A1CR_SS_DISABLE         (0x00000000u)
#define CSL_EMIF_A1CR_SS_ENABLE          (0x00000001u)

#define CSL_EMIF_A1CR_EW_MASK            (0x40000000u)
#define CSL_EMIF_A1CR_EW_SHIFT           (0x0000001Eu)
#define CSL_EMIF_A1CR_EW_RESETVAL        (0x00000000u)

/*----EW Tokens----*/
#define CSL_EMIF_A1CR_EW_DISABLE         (0x00000000u)
#define CSL_EMIF_A1CR_EW_ENABLE          (0x00000001u)

#define CSL_EMIF_A1CR_W_SETUP_MASK       (0x3C000000u)
#define CSL_EMIF_A1CR_W_SETUP_SHIFT      (0x0000001Au)
#define CSL_EMIF_A1CR_W_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A1CR_W_STROBE_MASK      (0x03F00000u)
#define CSL_EMIF_A1CR_W_STROBE_SHIFT     (0x00000014u)
#define CSL_EMIF_A1CR_W_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A1CR_W_HOLD_MASK        (0x000E0000u)
#define CSL_EMIF_A1CR_W_HOLD_SHIFT       (0x00000011u)
#define CSL_EMIF_A1CR_W_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A1CR_R_SETUP_MASK       (0x0001E000u)
#define CSL_EMIF_A1CR_R_SETUP_SHIFT      (0x0000000Du)
#define CSL_EMIF_A1CR_R_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A1CR_R_STROBE_MASK      (0x00001F80u)
#define CSL_EMIF_A1CR_R_STROBE_SHIFT     (0x00000007u)
#define CSL_EMIF_A1CR_R_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A1CR_R_HOLD_MASK        (0x00000070u)
#define CSL_EMIF_A1CR_R_HOLD_SHIFT       (0x00000004u)
#define CSL_EMIF_A1CR_R_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A1CR_TA_MASK            (0x0000000Cu)
#define CSL_EMIF_A1CR_TA_SHIFT           (0x00000002u)
#define CSL_EMIF_A1CR_TA_RESETVAL        (0x00000003u)

#define CSL_EMIF_A1CR_ASIZE_MASK         (0x00000003u)
#define CSL_EMIF_A1CR_ASIZE_SHIFT        (0x00000000u)
#define CSL_EMIF_A1CR_ASIZE_RESETVAL     (0x00000000u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_A1CR_ASIZE_8_BIT        (0x00000000u)
#define CSL_EMIF_A1CR_ASIZE_16_BIT       (0x00000001u)
#define CSL_EMIF_A1CR_ASIZE_32_BIT       (0x00000002u)
#define CSL_EMIF_A1CR_ASIZE_32_BIT       (0x00000002u)

#define CSL_EMIF_A1CR_RESETVAL           (0x3FFFFFFCu)

/* SDTIMR */

#define CSL_EMIF_SDTIMR_T_RFC_MASK       (0xF8000000u)
#define CSL_EMIF_SDTIMR_T_RFC_SHIFT      (0x0000001Bu)
#define CSL_EMIF_SDTIMR_T_RFC_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RP_MASK        (0x07000000u)
#define CSL_EMIF_SDTIMR_T_RP_SHIFT       (0x00000018u)
#define CSL_EMIF_SDTIMR_T_RP_RESETVAL    (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RCD_MASK       (0x00700000u)
#define CSL_EMIF_SDTIMR_T_RCD_SHIFT      (0x00000014u)
#define CSL_EMIF_SDTIMR_T_RCD_RESETVAL   (0x00000002u)

#define CSL_EMIF_SDTIMR_T_WR_MASK        (0x00070000u)
#define CSL_EMIF_SDTIMR_T_WR_SHIFT       (0x00000010u)
#define CSL_EMIF_SDTIMR_T_WR_RESETVAL    (0x00000001u)

#define CSL_EMIF_SDTIMR_T_RAS_MASK       (0x0000F000u)
#define CSL_EMIF_SDTIMR_T_RAS_SHIFT      (0x0000000Cu)
#define CSL_EMIF_SDTIMR_T_RAS_RESETVAL   (0x0000000Cu)

#define CSL_EMIF_SDTIMR_T_RC_MASK        (0x00000F00u)
#define CSL_EMIF_SDTIMR_T_RC_SHIFT       (0x00000008u)
#define CSL_EMIF_SDTIMR_T_RC_RESETVAL    (0x0000000Fu)

#define CSL_EMIF_SDTIMR_T_RRD_MASK       (0x00000070u)
#define CSL_EMIF_SDTIMR_T_RRD_SHIFT      (0x00000004u)
#define CSL_EMIF_SDTIMR_T_RRD_RESETVAL   (0x00000000u)