dsp281x_mcbsp.h

dsp ccs3.3 lcd keybord 适合初学

union XCERE_REG {
   Uint16              all;
   struct  XCERE_BITS  bit;
};  

// XCERF control register bit definitions:
struct  XCERF_BITS {         // bit description
   Uint16     XCERF0:1;       // 0   Receive Channel enable bit  
   Uint16     XCERF1:1;       // 1   Receive Channel enable bit  
   Uint16     XCERF2:1;       // 2   Receive Channel enable bit  
   Uint16     XCERF3:1;       // 3   Receive Channel enable bit   
   Uint16     XCERF4:1;       // 4   Receive Channel enable bit  
   Uint16     XCERF5:1;       // 5   Receive Channel enable bit  
   Uint16     XCERF6:1;       // 6   Receive Channel enable bit  
   Uint16     XCERF7:1;       // 7   Receive Channel enable bit 
   Uint16     XCERF8:1;       // 8   Receive Channel enable bit  
   Uint16     XCERF9:1;       // 9   Receive Channel enable bit  
   Uint16     XCERF10:1;      // 10  Receive Channel enable bit  
   Uint16     XCERF11:1;      // 11  Receive Channel enable bit 
   Uint16     XCERF12:1;      // 12  Receive Channel enable bit  
   Uint16     XCERF13:1;      // 13  Receive Channel enable bit  
   Uint16     XCERF14:1;      // 14  Receive Channel enable bit  
   Uint16     XCERF15:1;      // 15  Receive Channel enable bit 
}; 

union XCERF_REG {
   Uint16              all;
   struct  XCERF_BITS  bit;
};                   

// RCERG control register bit definitions:
struct  RCERG_BITS {         // bit description
   Uint16     RCEG0:1;       // 0   Receive Channel enable bit  
   Uint16     RCEG1:1;       // 1   Receive Channel enable bit  
   Uint16     RCEG2:1;       // 2   Receive Channel enable bit  
   Uint16     RCEG3:1;       // 3   Receive Channel enable bit   
   Uint16     RCEG4:1;       // 4   Receive Channel enable bit  
   Uint16     RCEG5:1;       // 5   Receive Channel enable bit  
   Uint16     RCEG6:1;       // 6   Receive Channel enable bit  
   Uint16     RCEG7:1;       // 7   Receive Channel enable bit 
   Uint16     RCEG8:1;       // 8   Receive Channel enable bit  
   Uint16     RCEG9:1;       // 9   Receive Channel enable bit  
   Uint16     RCEG10:1;      // 10  Receive Channel enable bit  
   Uint16     RCEG11:1;      // 11  Receive Channel enable bit 
   Uint16     RCEG12:1;      // 12  Receive Channel enable bit  
   Uint16     RCEG13:1;      // 13  Receive Channel enable bit  
   Uint16     RCEG14:1;      // 14  Receive Channel enable bit  
   Uint16     RCEG15:1;      // 15  Receive Channel enable bit 
}; 

union RCERG_REG {
   Uint16              all;
   struct  RCERG_BITS  bit;
};  

// RCERH control register bit definitions:
struct  RCERH_BITS {         // bit description
   Uint16     RCEH0:1;       // 0   Receive Channel enable bit  
   Uint16     RCEH1:1;       // 1   Receive Channel enable bit  
   Uint16     RCEH2:1;       // 2   Receive Channel enable bit  
   Uint16     RCEH3:1;       // 3   Receive Channel enable bit   
   Uint16     RCEH4:1;       // 4   Receive Channel enable bit  
   Uint16     RCEH5:1;       // 5   Receive Channel enable bit  
   Uint16     RCEH6:1;       // 6   Receive Channel enable bit  
   Uint16     RCEH7:1;       // 7   Receive Channel enable bit 
   Uint16     RCEH8:1;       // 8   Receive Channel enable bit  
   Uint16     RCEH9:1;       // 9   Receive Channel enable bit  
   Uint16     RCEH10:1;      // 10  Receive Channel enable bit  
   Uint16     RCEH11:1;      // 11  Receive Channel enable bit 
   Uint16     RCEH12:1;      // 12  Receive Channel enable bit  
   Uint16     RCEH13:1;      // 13  Receive Channel enable bit  
   Uint16     RCEH14:1;      // 14  Receive Channel enable bit  
   Uint16     RCEH15:1;      // 15  Receive Channel enable bit 
}; 

union RCERH_REG {
   Uint16              all;
   struct  RCERH_BITS  bit;
};

// XCERG control register bit definitions:
struct  XCERG_BITS {         // bit description
   Uint16     XCERG0:1;       // 0   Receive Channel enable bit  
   Uint16     XCERG1:1;       // 1   Receive Channel enable bit  
   Uint16     XCERG2:1;       // 2   Receive Channel enable bit  
   Uint16     XCERG3:1;       // 3   Receive Channel enable bit   
   Uint16     XCERG4:1;       // 4   Receive Channel enable bit  
   Uint16     XCERG5:1;       // 5   Receive Channel enable bit  
   Uint16     XCERG6:1;       // 6   Receive Channel enable bit  
   Uint16     XCERG7:1;       // 7   Receive Channel enable bit 
   Uint16     XCERG8:1;       // 8   Receive Channel enable bit  
   Uint16     XCERG9:1;       // 9   Receive Channel enable bit  
   Uint16     XCERG10:1;      // 10  Receive Channel enable bit  
   Uint16     XCERG11:1;      // 11  Receive Channel enable bit 
   Uint16     XCERG12:1;      // 12  Receive Channel enable bit  
   Uint16     XCERG13:1;      // 13  Receive Channel enable bit  
   Uint16     XCERG14:1;      // 14  Receive Channel enable bit  
   Uint16     XCERG15:1;      // 15  Receive Channel enable bit 
}; 

union XCERG_REG {
   Uint16              all;
   struct  XCERG_BITS  bit;
};  

// XCERH control register bit definitions:
struct  XCERH_BITS {         // bit description
   Uint16     XCEH0:1;       // 0   Receive Channel enable bit  
   Uint16     XCEH1:1;       // 1   Receive Channel enable bit  
   Uint16     XCEH2:1;       // 2   Receive Channel enable bit  
   Uint16     XCEH3:1;       // 3   Receive Channel enable bit   
   Uint16     XCEH4:1;       // 4   Receive Channel enable bit  
   Uint16     XCEH5:1;       // 5   Receive Channel enable bit  
   Uint16     XCEH6:1;       // 6   Receive Channel enable bit  
   Uint16     XCEH7:1;       // 7   Receive Channel enable bit 
   Uint16     XCEH8:1;       // 8   Receive Channel enable bit  
   Uint16     XCEH9:1;       // 9   Receive Channel enable bit  
   Uint16     XCEH10:1;      // 10  Receive Channel enable bit  
   Uint16     XCEH11:1;      // 11  Receive Channel enable bit 
   Uint16     XCEH12:1;      // 12  Receive Channel enable bit  
   Uint16     XCEH13:1;      // 13  Receive Channel enable bit  
   Uint16     XCEH14:1;      // 14  Receive Channel enable bit  
   Uint16     XCEH15:1;      // 15  Receive Channel enable bit 
}; 

union XCERH_REG {
   Uint16              all;
   struct  XCERH_BITS  bit;
};

// McBSP FIFO Transmit register bit definitions:
struct  MFFTX_BITS {            // bit   description
   Uint16     TXFFIL:5;         // 4:0   Interrupt level
   Uint16     TXFFIENA:1;       // 5     Interrupt enable
   Uint16     TXFFINT_CLEAR:1;  // 6     Clear INT flag
   Uint16     TXFFINT_FLAG:1;   // 7     INT flag
   Uint16     TXFFST:5;         // 12:8  FIFO status
   Uint16     TXFIFO_RESET:1;   // 13    FIFO reset
   Uint16     MFFENA:1;         // 14    Enhancement enable
   Uint16     rsvd:1;           // 15    reserved
}; 

union MFFTX_REG {
   Uint16            all;
   struct MFFTX_BITS bit;
};

// McBSP FIFO recieve register bit definitions:
struct  MFFRX_BITS {        // bits  description
   Uint16 RXFFIL:5;         // 4:0   Interrupt level
   Uint16 RXFFIENA:1;       // 5     Interrupt enable
   Uint16 RXFFINT_CLEAR:1;  // 6     Clear INT flag
   Uint16 RXFFINT_FLAG:1;   // 7     INT flag
   Uint16 RXFFST:5;         // 12:8  FIFO status
   Uint16 RXFIFO_RESET:1;   // 13    FIFO reset
   Uint16 RXFFOVF_CLEAR:1;  // 14    Clear overflow
   Uint16 RXFFOVF_FLAG:1;   // 15    FIFO overflow
}; 

union MFFRX_REG {
   Uint16            all;
   struct MFFRX_BITS bit;
};

// McBSP FIFO control register bit definitions:
struct  MFFCT_BITS {        // bits  description
    Uint16 FFTXTXDLY:8;     // 7:0   FIFO transmit delay
    Uint16 rsvd:7;          // 15:7  reserved
    Uint16 IACKM:1;         // 15    is IACK mode enable bit
};

union MFFCT_REG {
   Uint16             all;
   struct MFFCT_BITS  bit;
};
   
// McBSP FIFO INTERRUPT control register bit definitions:
struct  MFFINT_BITS {       // bits description
    Uint16     XINT:1;      // 0    XINT  interrupt enable
    Uint16     XEVTA:1;     // 1    XEVTA interrupt enable
    Uint16     RINT:1;      // 2    RINT  interrupt enable
    Uint16     REVTA:1;     // 3    REVTA interrupt enable
    Uint16     rsvd:12;     // 15:4 reserved
};

union MFFINT_REG {
   Uint16              all;
   struct MFFINT_BITS  bit;
};

// McBSP FIFO INTERRUPT status  register bit definitions:
struct  MFFST_BITS {       // bits description
    Uint16     EOBX:1;     // 0    EOBX flag
    Uint16     FSX:1;      // 1    FSX flag
    Uint16     EOBR:1;     // 2    EOBR flag
    Uint16     FSR:1;      // 3    FSR flag
    Uint16     rsvd:12;    // 15:4 reserved
};

union MFFST_REG {
   Uint16            all;
   struct MFFST_BITS bit;
};


//---------------------------------------------------------------------------
// McBSP Register File:
//
struct  MCBSP_REGS {      
   union DRR2_REG    DRR2;   // 0x7800, MCBSP Data receive register bits 31-16 
   union DRR1_REG    DRR1;   // 0x7801, MCBSP Data receive register bits 15-0 
   union DXR2_REG    DXR2;   // 0x7802, MCBSP Data transmit register bits 31-16 
   union DXR1_REG    DXR1;   // 0x7803, MCBSP Data transmit register bits 15-0 
   union SPCR2_REG   SPCR2;  // 0x7804, MCBSP control register bits 31-16 
   union SPCR1_REG   SPCR1;  // 0x7805, MCBSP control register bits 15-0 
   union RCR2_REG    RCR2;   // 0x7806, MCBSP receive control register bits 31-16 
   union RCR1_REG    RCR1;   // 0x7807, MCBSP receive control register bits 15-0 
   union XCR2_REG    XCR2;   // 0x7808, MCBSP transmit control register bits 31-16 
   union XCR1_REG    XCR1;   // 0x7809, MCBSP transmit control register bits 15-0 
   union SRGR2_REG   SRGR2;  // 0x7810, MCBSP sample rate gen register bits 31-16 
   union SRGR1_REG   SRGR1;  // 0x7811, MCBSP sample rate gen register bits 15-0  
   union MCR2_REG    MCR2;   // 0x7812, MCBSP multichannel register bits 31-16 
   union MCR1_REG    MCR1;   // 0x7813, MCBSP multichannel register bits 15-0    
   union RCERA_REG   RCERA;  // 0x7814, MCBSP Receive channel enable partition A 
   union RCERB_REG   RCERB;  // 0x7815, MCBSP Receive channel enable partition B 
   union XCERA_REG   XCERA;  // 0x7816, MCBSP Transmit channel enable partition A 
   union XCERB_REG   XCERB;  // 0x7817, MCBSP Transmit channel enable partition B            
   union PCR_REG     PCR;    // 0x7818, MCBSP Pin control register bits 15-0  
   union RCERC_REG   RCERC;  // 0x7819, MCBSP Receive channel enable partition C 
   union RCERD_REG   RCERD;  // 0x7820, MCBSP Receive channel enable partition D
   union XCERC_REG   XCERC;  // 0x7821, MCBSP Transmit channel enable partition C 
   union XCERD_REG   XCERD;  // 0x7823, MCBSP Transmit channel enable partition D             
   union RCERE_REG   RCERE;  // 0x7824, MCBSP Receive channel enable partition E 
   union RCERF_REG   RCERF;  // 0x7825, MCBSP Receive channel enable partition F
   union XCERE_REG   XCERE;  // 0x7826, MCBSP Transmit channel enable partition E
   union XCERF_REG   XCERF;  // 0x7827, MCBSP Transmit channel enable partition F            
   union RCERG_REG   RCERG;  // 0x7828, MCBSP Receive channel enable partition G
   union RCERH_REG   RCERH;  // 0x7829, MCBSP Receive channel enable partition H
   union XCERG_REG   XCERG;  // 0x7830, MCBSP Transmit channel enable partition G 
   union XCERH_REG   XCERH;  // 0x7831, MCBSP Transmit channel enable partition H             
   Uint16            rsvd1;  // 0x7832, reserved             
   union MFFTX_REG   MFFTX;  // 0x7833, MCBSP Transmit FIFO register bits  
   union MFFRX_REG   MFFRX;  // 0x7834, MCBSP Receive FIFO register bits
   union MFFCT_REG   MFFCT;  // 0x7835, MCBSP FIFO control register bits    
   union MFFINT_REG  MFFINT; // 0x7836, MCBSP Interrupt register bits  
   union MFFST_REG   MFFST;  // 0x7837, MCBSP Status register bits 
};

//---------------------------------------------------------------------------
// McBSP External References & Function Declarations:
//
extern volatile struct MCBSP_REGS McbspaRegs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  // end of DSP281x_MCBSP_H definition

//===========================================================================
// No more.
//===========================================================================