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📄 dsp281x_gpio.h

📁 dsp ccs3.3 lcd keybord 适合初学
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//                                     
//
struct GPDTOGGLE_BITS  {     // bits   description
   Uint16 GPIOD0:1;          // 0  
   Uint16 GPIOD1:1;          // 1 
   Uint16 rsvd1:3;           // 4:2  
   Uint16 GPIOD5:1;          // 5
   Uint16 GPIOD6:1;          // 6  
   Uint16 rsvd2:9;           // 15:7
};

union GPDTOGGLE_REG {
   Uint16                all;
   struct GPDTOGGLE_BITS bit;
};



//----------------------------------
// GPIOD Qualregister bit definitions
// 
//
struct GPDQUAL_BITS {    // bits   description
   Uint16 QUALPRD:8;     // 0:7    Qualification Sampling Period
   Uint16 rsvd1:8;       // 15:8   reserved
};    

union GPDQUAL_REG {
   Uint16              all;
   struct GPDQUAL_BITS bit;
};       


//---------------------------------------------
// GPIO E mux control register bit definitions
//                                     
//
struct GPEMUX_BITS  {                // bits  description
   Uint16 XINT1_XBIO_GPIOE0:1;       // 0  
   Uint16 XINT2_ADCSOC_GPIOE1:1;     // 1  
   Uint16 XNMI_XINT13_GPIOE2:1;      // 2 
   Uint16 rsvd1:12;                  // 15:3  
               
};

union GPEMUX_REG {
   Uint16             all;
   struct GPEMUX_BITS bit;
};

//---------------------------------------------------
// GPIO E Direction control register bit definitions
//                                     
//
struct GPEDIR_BITS  {        // bits   description
   Uint16 GPIOE0:1;          // 0 
   Uint16 GPIOE1:1;          // 1 
   Uint16 GPIOE2:1;          // 2 
   Uint16 rsvd1:12;          // 15:3        
};

union GPEDIR_REG {
   Uint16             all;
   struct GPEDIR_BITS bit;
};

//---------------------------------------------------
// GPIO E data register bit definitions
//                                     
//
struct GPEDAT_BITS  {        // bits   description
   Uint16 GPIOE0:1;          // 0 
   Uint16 GPIOE1:1;          // 1 
   Uint16 GPIOE2:1;          // 2 
   Uint16 rsvd1:12;          // 15:3        
};

union GPEDAT_REG {
   Uint16             all;
   struct GPEDAT_BITS bit;
};



//---------------------------------------------------
// GPIO E data set register bit definitions
//                                     
//
struct GPESET_BITS  {        // bits   description
   Uint16 GPIOE0:1;          // 0 
   Uint16 GPIOE1:1;          // 1 
   Uint16 GPIOE2:1;          // 2 
   Uint16 rsvd1:12;          // 15:3        
};

union GPESET_REG {
   Uint16             all;
   struct GPESET_BITS bit;
};


//---------------------------------------------------
// GPIO E data clear register bit definitions
//                                     
//
struct GPECLEAR_BITS  {      // bits   description
   Uint16 GPIOE0:1;          // 0 
   Uint16 GPIOE1:1;          // 1 
   Uint16 GPIOE2:1;          // 2 
   Uint16 rsvd1:12;          // 15:3        
};

union GPECLEAR_REG {
   Uint16               all;
   struct GPECLEAR_BITS bit;
};


//---------------------------------------------------
// GPIO E data toggle register bit definitions
//                                     
//
struct GPETOGGLE_BITS  {     // bits   description
   Uint16 GPIOE0:1;          // 0 
   Uint16 GPIOE1:1;          // 1 
   Uint16 GPIOE2:1;          // 2 
   Uint16 rsvd1:12;          // 15:3        
};

union GPETOGGLE_REG {
   Uint16                all;
   struct GPETOGGLE_BITS bit;
};



//-----------------------------------
// GPIOE Qualregister bit definitions 
// 
//
struct GPEQUAL_BITS {        // bits   description
   Uint16     QUALPRD:8;     // 0:7    Qualification Sampling Period
   Uint16 rsvd1:8;           // 15:8   reserved
};     

union GPEQUAL_REG {
   Uint16              all;
   struct GPEQUAL_BITS bit;
};      


//----------------------------------------------
//  GPIO F mux control register bit definitions
// 
//
struct GPFMUX_BITS  {      // bits   description
   Uint16 SPISIMOA_GPIOF0:1; // 0 
   Uint16 SPISOMIA_GPIOF1:1; // 1 
   Uint16 SPICLKA_GPIOF2:1;  // 2 
   Uint16 SPISTEA_GPIOF3:1;  // 3 
   Uint16 SCITXDA_GPIOF4:1;  // 4 
   Uint16 SCIRXDA_GPIOF5:1;  // 5 
   Uint16 CANTXA_GPIOF6:1;   // 6 
   Uint16 CANRXA_GPIOF7:1;   // 7 
   Uint16 MCLKXA_GPIOF8:1;   // 8 
   Uint16 MCLKRA_GPIOF9:1;   // 9 
   Uint16 MFSXA_GPIOF10:1;   // 10
   Uint16 MFSRA_GPIOF11:1;   // 11
   Uint16 MDXA_GPIOF12:1;    // 12
   Uint16 MDRA_GPIOF13:1;    // 13
   Uint16 XF_GPIOF14:1;      // 14
   Uint16 spare_GPIOF15:1;   // 15
         
};

/* Allow access to the bit fields or entire register */
union GPFMUX_REG {
   Uint16             all;
   struct GPFMUX_BITS bit;
};

//---------------------------------------------------
// GPIO F Direction control register bit definitions
//                                     
//
                                          
struct GPFDIR_BITS  {      // bits   description
   Uint16 GPIOF0:1;          // 0 
   Uint16 GPIOF1:1;          // 1 
   Uint16 GPIOF2:1;          // 2 
   Uint16 GPIOF3:1;          // 3 
   Uint16 GPIOF4:1;          // 4 
   Uint16 GPIOF5:1;          // 5 
   Uint16 GPIOF6:1;          // 6 
   Uint16 GPIOF7:1;          // 7 
   Uint16 GPIOF8:1;          // 8 
   Uint16 GPIOF9:1;          // 9 
   Uint16 GPIOF10:1;         // 10
   Uint16 GPIOF11:1;         // 11
   Uint16 GPIOF12:1;         // 12
   Uint16 GPIOF13:1;         // 13
   Uint16 GPIOF14:1;         // 14
   Uint16 GPIOF15:1;         // 15

};

union GPFDIR_REG {
   Uint16             all;
   struct GPFDIR_BITS bit;
};

//---------------------------------------------------
// GPIO F data register bit definitions
//                                     
//
                                          
struct GPFDAT_BITS  {      // bits   description
   Uint16 GPIOF0:1;          // 0 
   Uint16 GPIOF1:1;          // 1 
   Uint16 GPIOF2:1;          // 2 
   Uint16 GPIOF3:1;          // 3 
   Uint16 GPIOF4:1;          // 4 
   Uint16 GPIOF5:1;          // 5 
   Uint16 GPIOF6:1;          // 6 
   Uint16 GPIOF7:1;          // 7 
   Uint16 GPIOF8:1;          // 8 
   Uint16 GPIOF9:1;          // 9 
   Uint16 GPIOF10:1;         // 10
   Uint16 GPIOF11:1;         // 11
   Uint16 GPIOF12:1;         // 12
   Uint16 GPIOF13:1;         // 13
   Uint16 GPIOF14:1;         // 14
   Uint16 GPIOF15:1;         // 15

};

union GPFDAT_REG {
   Uint16             all;
   struct GPFDAT_BITS bit;
};


//---------------------------------------------------
// GPIO F data set register bit definitions
//                                     
//
                                          
struct GPFSET_BITS  {      // bits   description
   Uint16 GPIOF0:1;          // 0 
   Uint16 GPIOF1:1;          // 1 
   Uint16 GPIOF2:1;          // 2 
   Uint16 GPIOF3:1;          // 3 
   Uint16 GPIOF4:1;          // 4 
   Uint16 GPIOF5:1;          // 5 
   Uint16 GPIOF6:1;          // 6 
   Uint16 GPIOF7:1;          // 7 
   Uint16 GPIOF8:1;          // 8 
   Uint16 GPIOF9:1;          // 9 
   Uint16 GPIOF10:1;         // 10
   Uint16 GPIOF11:1;         // 11
   Uint16 GPIOF12:1;         // 12
   Uint16 GPIOF13:1;         // 13
   Uint16 GPIOF14:1;         // 14
   Uint16 GPIOF15:1;         // 15

};

union GPFSET_REG {
   Uint16             all;
   struct GPFSET_BITS bit;
};


//---------------------------------------------------
// GPIO F data clear register bit definitions
//                                     
//
                                          
struct GPFCLEAR_BITS  {    // bits   description
   Uint16 GPIOF0:1;          // 0 
   Uint16 GPIOF1:1;          // 1 
   Uint16 GPIOF2:1;          // 2 
   Uint16 GPIOF3:1;          // 3 
   Uint16 GPIOF4:1;          // 4 
   Uint16 GPIOF5:1;          // 5 
   Uint16 GPIOF6:1;          // 6 
   Uint16 GPIOF7:1;          // 7 
   Uint16 GPIOF8:1;          // 8 
   Uint16 GPIOF9:1;          // 9 
   Uint16 GPIOF10:1;         // 10
   Uint16 GPIOF11:1;         // 11
   Uint16 GPIOF12:1;         // 12
   Uint16 GPIOF13:1;         // 13
   Uint16 GPIOF14:1;         // 14
   Uint16 GPIOF15:1;         // 15

};

union GPFCLEAR_REG {
   Uint16               all;
   struct GPFCLEAR_BITS bit;
};


//---------------------------------------------------
// GPIO F data toggle register bit definitions
//                                     
//
                                          
struct GPFTOGGLE_BITS  {   // bits   description
   Uint16 GPIOF0:1;          // 0 
   Uint16 GPIOF1:1;          // 1 
   Uint16 GPIOF2:1;          // 2 
   Uint16 GPIOF3:1;          // 3 
   Uint16 GPIOF4:1;          // 4 
   Uint16 GPIOF5:1;          // 5 
   Uint16 GPIOF6:1;          // 6 
   Uint16 GPIOF7:1;          // 7 
   Uint16 GPIOF8:1;          // 8 
   Uint16 GPIOF9:1;          // 9 
   Uint16 GPIOF10:1;         // 10
   Uint16 GPIOF11:1;         // 11
   Uint16 GPIOF12:1;         // 12
   Uint16 GPIOF13:1;         // 13
   Uint16 GPIOF14:1;         // 14
   Uint16 GPIOF15:1;         // 15

};

union GPFTOGGLE_REG {
   Uint16                all;
   struct GPFTOGGLE_BITS bit;
};

//----------------------------------------------
//  GPIO G mux control register bit definitions
// 
//
struct GPGMUX_BITS  {      // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 SCITXDB_GPIOG4:1;  // 4 
   Uint16 SCIRXDB_GPIOG5:1;  // 5 
   Uint16 rsvd2:10;          // 15:6

};


/* Allow access to the bit fields or entire register */
union GPGMUX_REG {
   Uint16             all;
   struct GPGMUX_BITS bit;
};

//---------------------------------------------------
// GPIO G Direction control register bit definitions
//                                     
//
                                          
struct GPGDIR_BITS  {      // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 GPIOG4:1;          // 4 
   Uint16 GPIOG5:1;          // 5 
   Uint16 rsvd2:10;          // 15:6

};

union GPGDIR_REG {
   Uint16             all;
   struct GPGDIR_BITS bit;
};

//---------------------------------------------------
// GPIO G data register bit definitions
//                                     
//
                                          
struct GPGDAT_BITS  {      // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 GPIOG4:1;          // 4 
   Uint16 GPIOG5:1;          // 5 
   Uint16 rsvd2:10;          // 15:6

};

union GPGDAT_REG {
   Uint16             all;
   struct GPGDAT_BITS bit;
};


//---------------------------------------------------
// GPIO G data set register bit definitions
//                                     
//
                                          
struct GPGSET_BITS  {        // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 GPIOG4:1;          // 4 
   Uint16 GPIOG5:1;          // 5 
   Uint16 rsvd2:10;          // 15:6

};

union GPGSET_REG {
   Uint16             all;
   struct GPGSET_BITS bit;
};


//---------------------------------------------------
// GPIO G data clear register bit definitions
//                                     
//
                                          
struct GPGCLEAR_BITS  {      // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 GPIOG4:1;          // 4 
   Uint16 GPIOG5:1;          // 5 
   Uint16 rsvd2:10;          // 15:6

};

union GPGCLEAR_REG {
   Uint16               all;
   struct GPGCLEAR_BITS bit;
};


//---------------------------------------------------
// GPIO G data toggle register bit definitions
//                                     
//
                                          
struct GPGTOGGLE_BITS  {     // bits   description
   Uint16 rsvd1:4;           // 3:0
   Uint16 GPIOG4:1;          // 4 
   Uint16 GPIOG5:1;          // 5 
   Uint16 rsvd2:10;          // 15:6

};

union GPGTOGGLE_REG {
   Uint16                all;
   struct GPGTOGGLE_BITS bit;
};


struct GPIO_MUX_REGS {
   union  GPAMUX_REG   GPAMUX;
   union  GPADIR_REG   GPADIR;
   union  GPAQUAL_REG  GPAQUAL;
   Uint16              rsvd1;
   union  GPBMUX_REG   GPBMUX;
   union  GPBDIR_REG   GPBDIR;
   union  GPBQUAL_REG  GPBQUAL;   
   Uint16              rsvd2[5];
   union  GPDMUX_REG   GPDMUX;
   union  GPDDIR_REG   GPDDIR;
   union  GPDQUAL_REG  GPDQUAL;   
   Uint16              rsvd3;
   union  GPEMUX_REG   GPEMUX;
   union  GPEDIR_REG   GPEDIR;
   union  GPEQUAL_REG  GPEQUAL;   
   Uint16              rsvd4;
   union  GPFMUX_REG   GPFMUX;
   union  GPFDIR_REG   GPFDIR;
   Uint16              rsvd5[2];
   union  GPGMUX_REG   GPGMUX;
   union  GPGDIR_REG   GPGDIR;
   Uint16              rsvd6[6];
};

struct GPIO_DATA_REGS {
   union  GPADAT_REG    GPADAT;
   union  GPASET_REG    GPASET;
   union  GPACLEAR_REG  GPACLEAR;
   union  GPATOGGLE_REG GPATOGGLE;
   union  GPBDAT_REG    GPBDAT;
   union  GPBSET_REG    GPBSET;
   union  GPBCLEAR_REG  GPBCLEAR;
   union  GPBTOGGLE_REG GPBTOGGLE;
   Uint16               rsvd1[4];
   union  GPDDAT_REG    GPDDAT;
   union  GPDSET_REG    GPDSET;
   union  GPDCLEAR_REG  GPDCLEAR;
   union  GPDTOGGLE_REG GPDTOGGLE;
   union  GPEDAT_REG    GPEDAT;
   union  GPESET_REG    GPESET;
   union  GPECLEAR_REG  GPECLEAR;
   union  GPETOGGLE_REG GPETOGGLE;
   union  GPFDAT_REG    GPFDAT;
   union  GPFSET_REG    GPFSET;
   union  GPFCLEAR_REG  GPFCLEAR;
   union  GPFTOGGLE_REG GPFTOGGLE;
   union  GPGDAT_REG    GPGDAT;
   union  GPGSET_REG    GPGSET;
   union  GPGCLEAR_REG  GPGCLEAR;
   union  GPGTOGGLE_REG GPGTOGGLE;
   Uint16               rsvd2[4];      
};     
 

//---------------------------------------------------------------------------
// GPI/O External References & Function Declarations:
//
extern volatile struct GPIO_MUX_REGS GpioMuxRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  // end of DSP281x_GPIO_H definition

//===========================================================================
// No more.
//===========================================================================

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