m32r.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

   ; suffices.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 400))
					   (const_int 800))
				      (const_int 2)
				      (const_int 4)))])

(define_insn "*rev_branch_insn"
  [(set (pc)
	(if_then_else (match_operator 1 "eqne_comparison_operator"
				      [(reg 17) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
  ""
  "*
{
  static char instruction[40];
  sprintf (instruction, \"%s%s %%l0\",
	   (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
	   (get_attr_length (insn) == 2) ? \".s\" : \"\");
  return instruction;
}"
  [(set_attr "type" "branch")
   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
   ; lengths and insn alignments that are complex to track.
   ; It's not important that we be hyper-precise here.  It may be more
   ; important blah blah blah when the chip supports parallel execution
   ; blah blah blah but until then blah blah blah this is simple and
   ; suffices.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 400))
					   (const_int 800))
				      (const_int 2)
				      (const_int 4)))])

; reg/reg compare and branch insns

(define_insn "*reg_branch_insn"
  [(set (pc)
	(if_then_else (match_operator 1 "eqne_comparison_operator"
				      [(match_operand:SI 2 "register_operand" "r")
				       (match_operand:SI 3 "register_operand" "r")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  /* Is branch target reachable with beq/bne?  */
  if (get_attr_length (insn) == 4)
    {
      if (GET_CODE (operands[1]) == EQ)
	return \"beq %2,%3,%l0\";
      else
	return \"bne %2,%3,%l0\";
    }
  else
    {
      if (GET_CODE (operands[1]) == EQ)
	return \"bne %2,%3,1f\;bra %l0\;1:\";
      else
	return \"beq %2,%3,1f\;bra %l0\;1:\";
    }
}"
  [(set_attr "type" "branch")
  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
  ; which is complex to track and inaccurate length specs.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 25000))
					   (const_int 50000))
				      (const_int 4)
				      (const_int 8)))])

(define_insn "*rev_reg_branch_insn"
  [(set (pc)
	(if_then_else (match_operator 1 "eqne_comparison_operator"
				      [(match_operand:SI 2 "register_operand" "r")
				       (match_operand:SI 3 "register_operand" "r")])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
{
  /* Is branch target reachable with beq/bne?  */
  if (get_attr_length (insn) == 4)
    {
      if (GET_CODE (operands[1]) == NE)
	return \"beq %2,%3,%l0\";
      else
	return \"bne %2,%3,%l0\";
    }
  else
    {
      if (GET_CODE (operands[1]) == NE)
	return \"bne %2,%3,1f\;bra %l0\;1:\";
      else
	return \"beq %2,%3,1f\;bra %l0\;1:\";
    }
}"
  [(set_attr "type" "branch")
  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
  ; which is complex to track and inaccurate length specs.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 25000))
					   (const_int 50000))
				      (const_int 4)
				      (const_int 8)))])

; reg/zero compare and branch insns

(define_insn "*zero_branch_insn"
  [(set (pc)
	(if_then_else (match_operator 1 "signed_comparison_operator"
				      [(match_operand:SI 2 "register_operand" "r")
				       (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  const char *br,*invbr;
  char asmtext[40];

  switch (GET_CODE (operands[1]))
    {
      case EQ : br = \"eq\"; invbr = \"ne\"; break;
      case NE : br = \"ne\"; invbr = \"eq\"; break;
      case LE : br = \"le\"; invbr = \"gt\"; break;
      case GT : br = \"gt\"; invbr = \"le\"; break;
      case LT : br = \"lt\"; invbr = \"ge\"; break;
      case GE : br = \"ge\"; invbr = \"lt\"; break;

      default: abort();
    }

  /* Is branch target reachable with bxxz?  */
  if (get_attr_length (insn) == 4)
    {
      sprintf (asmtext, \"b%sz %%2,%%l0\", br);
      output_asm_insn (asmtext, operands);
    }
  else
    {
      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
      output_asm_insn (asmtext, operands);
    }
  return \"\";
}"
  [(set_attr "type" "branch")
  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
  ; which is complex to track and inaccurate length specs.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 25000))
					   (const_int 50000))
				      (const_int 4)
				      (const_int 8)))])

(define_insn "*rev_zero_branch_insn"
  [(set (pc)
	(if_then_else (match_operator 1 "eqne_comparison_operator"
				      [(match_operand:SI 2 "register_operand" "r")
				       (const_int 0)])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "*
{
  const char *br,*invbr;
  char asmtext[40];

  switch (GET_CODE (operands[1]))
    {
      case EQ : br = \"eq\"; invbr = \"ne\"; break;
      case NE : br = \"ne\"; invbr = \"eq\"; break;
      case LE : br = \"le\"; invbr = \"gt\"; break;
      case GT : br = \"gt\"; invbr = \"le\"; break;
      case LT : br = \"lt\"; invbr = \"ge\"; break;
      case GE : br = \"ge\"; invbr = \"lt\"; break;

      default: abort();
    }

  /* Is branch target reachable with bxxz?  */
  if (get_attr_length (insn) == 4)
    {
      sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
      output_asm_insn (asmtext, operands);
    }
  else
    {
      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
      output_asm_insn (asmtext, operands);
    }
  return \"\";
}"
  [(set_attr "type" "branch")
  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
  ; which is complex to track and inaccurate length specs.
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 25000))
					   (const_int 50000))
				      (const_int 4)
				      (const_int 8)))])

;; S<cc> operations to set a register to 1/0 based on a comparison

(define_expand "seq"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (TARGET_M32RX)
    {
      if (! reg_or_zero_operand (op2, mode))
        op2 = force_reg (mode, op2);

      emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
      DONE;
    }
  if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
    {
      emit_insn (gen_seq_zero_insn (op0, op1));
      DONE;
    }

  if (! reg_or_eq_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_seq_insn (op0, op1, op2));
  DONE;
}")

(define_insn "seq_insn_m32rx"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(eq:SI (match_operand:SI 1 "register_operand" "%r")
	       (match_operand:SI 2 "reg_or_zero_operand" "rP")))
   (clobber (reg:SI 17))]
  "TARGET_M32RX"
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "6")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(eq:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_zero_operand" "")))
   (clobber (reg:SI 17))]
  "TARGET_M32RX"
  [(set (reg:SI 17)
	(eq:SI (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))]
  "")

(define_insn "seq_zero_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(eq:SI (match_operand:SI 1 "register_operand" "r")
	       (const_int 0)))
   (clobber (reg:SI 17))]
  "TARGET_M32R"
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "6")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(eq:SI (match_operand:SI 1 "register_operand" "")
	       (const_int 0)))
   (clobber (reg:SI 17))]
  "TARGET_M32R"
  [(match_dup 3)]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];

  start_sequence ();
  emit_insn (gen_cmp_ltusi_insn (op1, GEN_INT (1)));
  emit_insn (gen_movcc_insn (op0));
  operands[3] = get_insns ();
  end_sequence ();
}")

(define_insn "seq_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
   (clobber (reg:SI 17))
   (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
  "TARGET_M32R"
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8,8,10,10")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(eq:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
   (clobber (reg:SI 17))
   (clobber (match_scratch:SI 3 ""))]
  "TARGET_M32R && reload_completed"
  [(match_dup 4)]
  "
{
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx op3 = operands[3];
  HOST_WIDE_INT value;

  if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
      && REGNO (op2) == REGNO (op3))
    {
      op1 = operands[2];
      op2 = operands[1];
    }

  start_sequence ();
  if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
      && REGNO (op1) != REGNO (op3))
    {
      emit_move_insn (op3, op1);
      op1 = op3;
    }

  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
      && CMP_INT16_P (value))
    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
  else
    emit_insn (gen_xorsi3 (op3, op1, op2));

  emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));
  emit_insn (gen_movcc_insn (op0));
  operands[4] = get_insns ();
  end_sequence ();
}")

(define_expand "sne"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (GET_CODE (op2) != CONST_INT
      || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
    {
      rtx reg;

      if (reload_completed || reload_in_progress)
	FAIL;

      reg = gen_reg_rtx (SImode);
      emit_insn (gen_xorsi3 (reg, op1, op2));
      op1 = reg;

      if (! register_operand (op1, mode))
        op1 = force_reg (mode, op1);

      emit_insn (gen_sne_zero_insn (op0, op1));
      DONE;
    }
  else
    FAIL;
}")

(define_insn "sne_zero_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ne:SI (match_operand:SI 1 "register_operand" "r")
	       (const_int 0)))
   (clobber (reg:SI 17))
   (clobber (match_scratch:SI 2 "=&r"))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "6")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ne:SI (match_operand:SI 1 "register_operand" "")
	       (const_int 0)))
   (clobber (reg:SI 17))
   (clobber (match_scratch:SI 2 ""))]
  "reload_completed"
  [(set (match_dup 2)
	(const_int 0))
   (set (reg:SI 17)
	(ltu:SI (match_dup 2)
		(match_dup 1)))
   (set (match_dup 0)
	(reg:SI 17))]
  "")
	
(define_expand "slt"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_slt_insn (op0, op1, op2));
  DONE;
}")

(define_insn "slt_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(lt:SI (match_operand:SI 1 "register_operand" "r,r")
	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:SI 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "4,6")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(lt:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:SI 17))]
  ""
  [(set (reg:SI 17)
	(lt:SI (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(reg:SI 17))]
  "")

(define_expand "sle"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;