h8300.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

      if (GET_CODE (operands[1]) == MEM)
	{
	  rtx inside = XEXP (operands[1], 0);
	  if (REG_P (inside))
	    {
	      rn = REGNO (inside);
	    }
	  else if (GET_CODE (inside) == PLUS)
	    {
	      rtx lhs = XEXP (inside, 0);
	      rtx rhs = XEXP (inside, 1);
	      if (REG_P (lhs)) rn = REGNO (lhs);
	      if (REG_P (rhs)) rn = REGNO (rhs);
	    }
	}
      if (rn == REGNO (operands[0]))
	/* Move the second word first.  */
	return \"mov.w	%f1,%f0\;mov.w	%e1,%e0\";
      else
	/* Move the first word first.  */
	return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";

    case 3:
      return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
    case 4:
      return \"mov.w	%f1,%T0\;mov.w	%e1,%T0\";
    case 5:
      return \"mov.w	%T1,%e0\;mov.w	%T1,%f0\";
    default:
      abort ();
    }
}"
  [(set_attr "length" "4,4,8,8,4,4")
   (set_attr "cc" "clobber")])

(define_insn "movsi_h8300hs"
  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
	(match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
  "(TARGET_H8300S || TARGET_H8300H)
   && (register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))
   && !(GET_CODE (operands[0]) == MEM
	&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
	&& GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
	&& GET_CODE (operands[1]) == REG
	&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"sub.l	%S0,%S0\";
    case 7:
      return \"clrmac\";
    case 8:
      return \"clrmac\;ldmac %1,macl\";
    case 9:
      return \"stmac	macl,%0\";
    default:
      if (GET_CODE (operands[1]) == CONST_INT)
	{
	  int val = INTVAL (operands[1]);

	  /* Look for constants which can be made by adding an 8-bit
	     number to zero in one of the two low bytes.  */
	  if (val == (val & 0xff))
	    {
	      operands[1] = GEN_INT ((char) val & 0xff);
	      return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
	    }

	  if (val == (val & 0xff00))
	    {
	      operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
	      return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
	    }

	  /* Look for constants that can be obtained by subs, inc, and
	     dec to 0.  */
	  switch (val & 0xffffffff)
	    {
	    case 0xffffffff:
	      return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
	    case 0xfffffffe:
	      return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
	    case 0xfffffffc:
	      return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";

	    case 0x0000ffff:
	      return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
	    case 0x0000fffe:
	      return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";

	    case 0xffff0000:
	      return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
	    case 0xfffe0000:
	      return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";

	    case 0x00010000:
	      return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
	    case 0x00020000:
	      return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
	    }
	}
    }
   return \"mov.l	%S1,%S0\";
}"
  [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
   (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])

(define_insn "movsf_h8300h"
  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
	(match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
  "(TARGET_H8300H || TARGET_H8300S)
   && (register_operand (operands[0], SFmode)
       || register_operand (operands[1], SFmode))"
  "@
   sub.l	%S0,%S0
   mov.l	%S1,%S0
   mov.l	%S1,%S0
   mov.l	%S1,%S0
   mov.l	%S1,%S0
   mov.l	%S1,%S0"
  [(set_attr "length" "2,2,10,10,4,4")
   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])

;; ----------------------------------------------------------------------
;; TEST INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
			       (const_int 1)
			       (match_operand 1 "const_int_operand" "n,n")))]
  "TARGET_H8300"
  "btst	%Z1,%Y0"
  [(set_attr "length" "2,4")
   (set_attr "cc" "set_zn,set_zn")])

(define_insn ""
  [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
			       (const_int 1)
			       (match_operand 1 "const_int_operand" "n")))]
  "TARGET_H8300"
  "btst	%Z1,%Y0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn "*tst_extzv_bitqi_1_n"
  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
			       (const_int 1)
			       (match_operand 1 "const_int_operand" "n,n")))]
  "(TARGET_H8300H || TARGET_H8300S)
   && INTVAL (operands[1]) != 7"
  "btst	%Z1,%Y0"
  [(set_attr "length" "2,8")
   (set_attr "cc" "set_zn,set_zn")])

(define_insn_and_split "*tst_extzv_memqi_1_n"
  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
			       (const_int 1)
			       (match_operand 1 "const_int_operand" "n")))
   (clobber (match_scratch:QI 2 "=&r"))]
  "(TARGET_H8300H || TARGET_H8300S)
   && !EXTRA_CONSTRAINT (operands[0], 'U')
   && INTVAL (operands[1]) != 7"
  "#"
  "&& reload_completed"
  [(set (match_dup 2)
	(match_dup 0))
   (set (cc0) (zero_extract:SI (match_dup 2)
			       (const_int 1)
			       (match_dup 1)))]
  "")

(define_insn ""
  [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
			       (const_int 1)
			       (match_operand 1 "const_int_operand" "n")))]
  "(TARGET_H8300H || TARGET_H8300S)
   && INTVAL (operands[1]) <= 15"
  "btst	%Z1,%Y0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn ""
  [(set (cc0)
	(and:HI (match_operand:HI 0 "register_operand" "r")
		(match_operand:HI 1 "single_one_operand" "n")))]
  ""
  "*
{
  operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
  if (INTVAL (operands[1]) > 128)
    {
      operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
      return \"btst\\t%V1,%t0\";
    }
  return \"btst\\t%V1,%s0\";
}"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "single_one_operand" "n")))]
  "(TARGET_H8300H || TARGET_H8300S)
   && (INTVAL (operands[1]) & 0xffff) != 0"
  "*
{
  operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
  if (INTVAL (operands[1]) > 128)
    {
      operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
      return \"btst\\t%V1,%x0\";
    }
  return \"btst\\t%V1,%w0\";
}"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn "tstqi"
  [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
  ""
  "mov.b	%X0,%X0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

(define_insn "tsthi"
  [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
  ""
  "mov.w	%T0,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

(define_insn ""
  [(set (cc0)
	(and:HI (match_operand:HI 0 "register_operand" "r")
		(const_int -256)))]
  ""
  "mov.b	%t0,%t0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

(define_insn "tstsi"
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
  "TARGET_H8300H || TARGET_H8300S"
  "mov.l	%S0,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "register_operand" "r")
		(const_int -65536)))]
  ""
  "mov.w	%e0,%e0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

(define_insn "cmpqi"
  [(set (cc0)
	(compare:QI (match_operand:QI 0 "register_operand" "r")
		    (match_operand:QI 1 "nonmemory_operand" "rn")))]
  ""
  "cmp.b	%X1,%X0"
  [(set_attr "length" "2")
   (set_attr "cc" "compare")])

(define_expand "cmphi"
  [(set (cc0)
	(compare:HI (match_operand:HI 0 "register_operand" "")
		    (match_operand:HI 1 "nonmemory_operand" "")))]
  ""
  "
{
  /* Force operand1 into a register if we're compiling
     for the H8/300.  */
  if (GET_CODE (operands[1]) != REG && TARGET_H8300)
    operands[1] = force_reg (HImode, operands[1]);
}")

(define_insn ""
  [(set (cc0)
	(compare:HI (match_operand:HI 0 "register_operand" "r")
		    (match_operand:HI 1 "register_operand" "r")))]
  "TARGET_H8300"
  "cmp.w	%T1,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "compare")])

(define_insn ""
  [(set (cc0)
	(compare:HI (match_operand:HI 0 "register_operand" "r,r")
		    (match_operand:HI 1 "nonmemory_operand" "r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "cmp.w	%T1,%T0"
  [(set_attr "length" "2,4")
   (set_attr "cc" "compare,compare")])

(define_insn "cmpsi"
  [(set (cc0)
	(compare:SI (match_operand:SI 0 "register_operand" "r,r")
		    (match_operand:SI 1 "nonmemory_operand" "r,i")))]
  "TARGET_H8300H || TARGET_H8300S"
  "cmp.l	%S1,%S0"
  [(set_attr "length" "2,6")
   (set_attr "cc" "compare,compare")])

;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "addqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(plus:QI (match_operand:QI 1 "register_operand" "%0")
		 (match_operand:QI 2 "nonmemory_operand" "rn")))]
  ""
  "add.b	%X2,%X0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_expand "addhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(plus:HI (match_operand:HI 1 "register_operand" "")
		 (match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn "*addhi3_h8300"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
		 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
  "TARGET_H8300"
  "@
   adds	%2,%T0
   subs	%G2,%T0
   add.b	%t2,%t0
   add.b	%s2,%s0\;addx	%t2,%t0
   add.w	%T2,%T0"
  [(set_attr "length" "2,2,2,4,2")
   (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])

;; This splitter is very important to make the stack adjustment
;; interrupt-safe.  The combination of add.b and addx is unsafe!
;;
;; We apply this split after the peephole2 pass so that we won't end
;; up creating too many adds/subs when a scratch register is
;; available, which is actually a common case because stack unrolling
;; tends to happen immediately after a function call.

(define_split
  [(set (match_operand:HI 0 "stack_pointer_operand" "")
	(plus:HI (match_dup 0)
		 (match_operand 1 "const_int_gt_2_operand" "")))]
  "TARGET_H8300 && flow2_completed"
  [(const_int 0)]
  "split_adds_subs (HImode, operands); DONE;")

(define_peephole2
  [(match_scratch:HI 2 "r")
   (set (match_operand:HI 0 "stack_pointer_operand" "")
	(plus:HI (match_dup 0)
		 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
  "TARGET_H8300"
  [(set (match_dup 2)
	(match_dup 1))
   (set (match_dup 0)
	(plus:HI (match_dup 0)
		 (match_dup 2)))]
  "")

(define_insn "*addhi3_h8300hs"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
		 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
  "TARGET_H8300H || TARGET_H8300S"
  "@
   adds	%2,%S0
   subs	%G2,%S0
   add.b	%t2,%t0
   add.w	%T2,%T0
   add.w	%T2,%T0"
  [(set_attr "length" "2,2,2,4,2")
   (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])

(define_split
  [(set (match_operand:HI 0 "register_operand" "")
	(plus:HI (match_dup 0)
		 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
  ""
  [(const_int 0)]
  "split_adds_subs (HImode, operands); DONE;")

(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "register_operand" "")
		 (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn "addsi_h8300"
  [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
		 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
  "TARGET_H8300"
  "@
   add	%w2,%w0\;addx	%x2,%x0\;addx	%y2,%y0\;addx	%z2,%z0
   add.w	%f2,%f0\;addx	%y2,%y0\;addx	%z2,%z0
   mov.w	%f1,%f0\;mov.w	%e1,%e0\;add.w	%f2,%f0\;addx	%y2,%y0\;addx	%z2,%z0"
  [(set_attr "length" "8,6,10")
   (set_attr "cc" "clobber")])

(define_insn "addsi_h8300h"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
		 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
  "TARGET_H8300H || TARGET_H8300S"
  "@
   adds	%2,%S0
   subs	%G2,%S0
   add.l	%S2,%S0
   add.l	%S2,%S0"
  [(set_attr "length" "2,2,6,2")
   (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_dup 0)
		 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  [(const_int 0)]
  "split_adds_subs (SImode, operands); DONE;")

;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------