m68hc11.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

  "@
   clra\\n\\tclrb
   ld%0\\t#0
   clr\\t%b0\\n\\tclr\\t%h0")

(define_insn "*movhi_68hc12"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,U,U,m,!u")
	(match_operand:HI 1 "general_operand" "U,rim,dAwi,!u,dAw,riU"))]
  "TARGET_M6812"
  "*
{
  m68hc11_gen_movhi (insn, operands);
  return \"\";
}")

(define_insn "*movhi_m68hc11"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=dAw,!u,m,m,dAw,!*u")
	(match_operand:HI 1 "general_operand" "dAwim,dAw,dA,?Aw,!*u,dAw"))]
  "TARGET_M6811"
  "*
{
  m68hc11_gen_movhi (insn, operands);
  return \"\";
}")

;;--------------------------------------------------------------------
;;- 8-bit Move Operations.
;; We don't need a scratch register.
;;--------------------------------------------------------------------
;;
;; The *a alternative also clears the high part of the register.
;; This should be ok since this is not the (strict_low_part) set.
;;
(define_insn "movqi_const0"
  [(set (match_operand:QI 0 "non_push_operand" "=d,m,!u,*A,!*q")
	(const_int 0))]
  ""
  "@
   clrb
   clr\\t%b0
   clr\\t%b0
   ld%0\\t#0
   clr%0")

;;
;; 8-bit operations on address registers.
;;
;; Switch temporary to the D register and load the value in B.
;; This is possible as long as the address register does not
;; appear in the source operand.
;;
(define_split
  [(set (match_operand:QI 0 "hard_addr_reg_operand" "")
        (match_operand:QI 1 "general_operand" ""))]
  "z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode
   && !reg_mentioned_p (operands[0], operands[1])
   && !D_REG_P (operands[1])"
  [(parallel [(set (reg:HI D_REGNUM) (match_dup 2))
              (set (match_dup 2) (reg:HI D_REGNUM))])
   (set (reg:QI D_REGNUM) (match_dup 1))
   (parallel [(set (reg:HI D_REGNUM) (match_dup 2))
              (set (match_dup 2) (reg:HI D_REGNUM))])]
  "operands[2] = gen_rtx (REG, HImode, REGNO (operands[0]));")

;;
;; 8-bit operations on address registers.
;;
(define_split
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
        (match_operand:QI 1 "hard_addr_reg_operand" ""))]
  "z_replacement_completed == 2 && GET_MODE (operands[1]) == QImode
   && !reg_mentioned_p (operands[1], operands[0])
   && !D_REG_P (operands[0])"
  [(parallel [(set (reg:HI D_REGNUM) (match_dup 2))
              (set (match_dup 2) (reg:HI D_REGNUM))])
   (set (match_dup 0) (reg:QI D_REGNUM))
   (parallel [(set (reg:HI D_REGNUM) (match_dup 2))
              (set (match_dup 2) (reg:HI D_REGNUM))])]
  "operands[2] = gen_rtx (REG, HImode, REGNO (operands[1]));")

(define_insn "*movqi2_push"
  [(set (match_operand:QI 0 "push_operand" "=<,<")
	(match_operand:QI 1 "general_operand" "d,!*A"))]
  ""
  "*
{
  if (A_REG_P (operands[1]))
    return \"#\";

  cc_status = cc_prev_status;
  return \"pshb\";
}")


(define_expand "movqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (reload_in_progress)
    {
      if (m68hc11_reload_operands (operands))
        {
          DONE;
        }
    }
  if (TARGET_M6811 && (reload_in_progress | reload_completed) == 0)
    {
      if (GET_CODE (operands[0]) == MEM
	  && (GET_CODE (operands[1]) == MEM
	      || GET_CODE (operands[1]) == CONST_INT))
        {
	  operands[1] = force_reg (QImode, operands[1]);
        }
      else if (IS_STACK_PUSH (operands[0])
	       && GET_CODE (operands[1]) != REG)
        {
	  operands[1] = force_reg (QImode, operands[1]);
        }
    }
  /* For push/pop, emit a REG_INC note to make sure the reload
     inheritance and reload CSE pass notice the change of the stack
     pointer.  */
  if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
    {
      rtx insn;

      insn = emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
      REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
					  stack_pointer_rtx,
					  REG_NOTES (insn));
      DONE;
    }
}")

(define_insn "*movqi_68hc12"
  [(set (match_operand:QI 0 "nonimmediate_operand" 
				"=U,d*AU*q,d*A*qU,d*A*q,m,?*u,m")
	(match_operand:QI 1 "general_operand" 
				"U,*ri*q,U,m,d*q,*ri*qU,!*A"))]
  "TARGET_M6812"
  "*
{
  m68hc11_gen_movqi (insn, operands);
  return \"\";
}")

(define_insn "*movqi_m68hc11"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d*A*q,m,m,d*A*q,*u")
	(match_operand:QI 1 "general_operand" "d*Aim*q,d*q,!*A,*u,d*A*q"))]
  "TARGET_M6811"
  "*
{
  m68hc11_gen_movqi (insn, operands);
  return \"\";
}")

;;--------------------------------------------------------------------
;;-  Swap registers
;;--------------------------------------------------------------------
;; Swapping registers is used for split patterns.
(define_insn "swap_areg"
   [(set (match_operand:HI 0 "hard_reg_operand" "=d,A")
         (match_operand:HI 1 "hard_reg_operand" "=A,d"))
    (set (match_dup 1) (match_dup 0))]
   ""
   "*
{
  m68hc11_output_swap (insn, operands);
  return \"\";
}")

;;--------------------------------------------------------------------
;;-  Truncation insns.
;;--------------------------------------------------------------------
;;
;; Truncation are not necessary because GCC knows how to truncate,
;; specially when values lie in consecutive registers.
;;

(define_expand "floatunssisf2"
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
	(unsigned_float:SF (match_operand:SI 1 "general_operand" "")))]
  ""
  "m68hc11_emit_libcall (\"__floatunsisf\", UNSIGNED_FLOAT, 
			 SFmode, SImode, 2, operands);
   DONE;")

(define_expand "floatunssidf2"
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
	(unsigned_float:DF (match_operand:SI 1 "general_operand" "")))]
  ""
  "m68hc11_emit_libcall (\"__floatunsidf\", UNSIGNED_FLOAT, 
			 DFmode, SImode, 2, operands);
   DONE;")

;;--------------------------------------------------------------------
;;-  Zero extension insns.
;;--------------------------------------------------------------------

;;
;; 64-bit extend.  The insn will be split into 16-bit instructions just
;; before the final pass.  We need a scratch register for the split.
;; The final value can be generated on the stack directly.  This is more
;; efficient and useful for conversions made during parameter passing rules.
;;
(define_insn "zero_extendqidi2"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,!u,m,!u")
	(zero_extend:DI 
	   (match_operand:QI 1 "nonimmediate_operand" "m,dmu,*B,*B")))
   (clobber (match_scratch:HI 2 "=&d,&dB,&d,&dB"))]
  ""
  "#")

(define_split
  [(set (match_operand:DI 0 "push_operand" "")
	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))
   (clobber (match_scratch:HI 2 "=&dB"))]
  "z_replacement_completed == 2"
  [(const_int 0)]
  "
{
  rtx low  = m68hc11_gen_lowpart (SImode, operands[0]);
  rtx push = m68hc11_gen_lowpart (HImode, low);
  rtx src  = operands[1];

   /* Source operand must be in a hard register.  */
   if (!H_REG_P (src))
     {
       src = gen_rtx (REG, QImode, REGNO (operands[2]));
       emit_move_insn (src, operands[1]);
     }

   /* Source is in D, we can push B then one word of 0 and we do
      a correction on the stack pointer.  */
   if (D_REG_P (src))
     {
       emit_move_insn (m68hc11_gen_lowpart (QImode, push), src);
       emit_move_insn (operands[2], const0_rtx);
       if (D_REG_P (operands[2]))
	 {
	   emit_move_insn (m68hc11_gen_lowpart (QImode, push), src);
	 }
       else
	 {
           emit_move_insn (push, operands[2]);
           emit_insn (gen_addhi3 (gen_rtx (REG, HImode, HARD_SP_REGNUM),
				  gen_rtx (REG, HImode, HARD_SP_REGNUM),
			          const1_rtx));
	 }
     }
   else
     {
       /* Source is in X or Y.  It's better to push the 16-bit register
          and then to some stack adjustment.  */
       src = gen_rtx (REG, HImode, REGNO (src));
       emit_move_insn (push, src);
       emit_move_insn (operands[2], const0_rtx);
       emit_insn (gen_addhi3 (gen_rtx (REG, HImode, HARD_SP_REGNUM),
			      gen_rtx (REG, HImode, HARD_SP_REGNUM),
			      const1_rtx));
       emit_move_insn (push, operands[2]);
       emit_insn (gen_addhi3 (gen_rtx (REG, HImode, HARD_SP_REGNUM),
			      gen_rtx (REG, HImode, HARD_SP_REGNUM),
			      const1_rtx));
     }      
   emit_move_insn (push, operands[2]);
   emit_move_insn (push, operands[2]);
   emit_move_insn (push, operands[2]);
   DONE;
}")

(define_split
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))
   (clobber (match_scratch:HI 2 "=&dB"))]
  "z_replacement_completed == 2"
  [(const_int 0)]
  "
{
  rtx low  = m68hc11_gen_lowpart (SImode, operands[0]);
  rtx low2 = m68hc11_gen_lowpart (HImode, low);
  rtx src  = operands[1];

   /* Source operand must be in a hard register.  */
   if (!H_REG_P (src))
     {
       src = gen_rtx (REG, QImode, REGNO (operands[2]));
       emit_move_insn (src, operands[1]);
     }

   emit_move_insn (m68hc11_gen_lowpart (QImode, low2), src);
   emit_move_insn (operands[2], const0_rtx);
   src = gen_rtx (REG, QImode, REGNO (operands[2]));
   emit_move_insn (m68hc11_gen_highpart (QImode, low2), src);

   emit_move_insn (m68hc11_gen_highpart (HImode, low), operands[2]);
   low = m68hc11_gen_highpart (SImode, operands[0]);
   emit_move_insn (m68hc11_gen_lowpart (HImode, low), operands[2]);
   emit_move_insn (m68hc11_gen_highpart (HImode, low), operands[2]);
   DONE;
}")

(define_insn "zero_extendhidi2"
  [(set (match_operand:DI 0 "non_push_operand" "=m,m,m,m,!u,!u")
	(zero_extend:DI 
	    (match_operand:HI 1 "nonimmediate_operand" "m,d,A,!u,dmA,!u")))
   (clobber (match_scratch:HI 2 "=&d,&B,&d,&dB,&dB,&dB"))]
  ""
  "#")

(define_split
  [(set (match_operand:DI 0 "non_push_operand" "")
	(zero_extend:DI 
	    (match_operand:HI 1 "nonimmediate_operand" "")))
   (clobber (match_scratch:HI 2 ""))]
  "z_replacement_completed == 2"
  [(const_int 0)]
  "
{
   rtx low  = m68hc11_gen_lowpart (SImode, operands[0]);
   rtx high = m68hc11_gen_highpart (SImode, operands[0]);
   rtx src  = operands[1];

   /* Make sure the source is in a hard register.  */
   if (!H_REG_P (src))
     {
       src = operands[2];
       emit_move_insn (src, operands[1]);
     }

   /* Move the low part first for the push.  */
   emit_move_insn (m68hc11_gen_lowpart (HImode, low), src);

   /* Now, use the scratch register to fill in the zeros.  */
   emit_move_insn (operands[2], const0_rtx);
   emit_move_insn (m68hc11_gen_highpart (HImode, low), operands[2]);
   emit_move_insn (m68hc11_gen_lowpart (HImode, high), operands[2]);
   emit_move_insn (m68hc11_gen_highpart (HImode, high), operands[2]);
   DONE;
}")

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,m,!u,!u")
	(zero_extend:DI 
	    (match_operand:SI 1 "nonimmediate_operand" "m,Du,m,Du")))
   (clobber (match_scratch:HI 2 "=d,d,d,d"))]
  ""
  "#")

(define_split 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(zero_extend:DI 
	    (match_operand:SI 1 "nonimmediate_operand" "")))
   (clobber (match_scratch:HI 2 ""))]
  "z_replacement_completed == 2"
  [(const_int 0)]
  "
{
  rtx low  = m68hc11_gen_lowpart (SImode, operands[0]);
  rtx high = m68hc11_gen_highpart (SImode, operands[0]);

  /* Move the low part first so that this is ok for a push.  */
  m68hc11_split_move (low, operands[1], operands[2]);

  /* Use the scratch register to clear the high part of the destination.  */
  emit_move_insn (operands[2], const0_rtx);
  emit_move_insn (m68hc11_gen_lowpart (HImode, high), operands[2]);
  emit_move_insn (m68hc11_gen_highpart (HImode, high), operands[2]);
  DONE;
}")

;;
;; For 16->32bit unsigned extension, we don't allow generation on the stack
;; because it's less efficient.
;;
(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "non_push_operand" "=D,m,u,m,m,!u,!u")
        (zero_extend:SI 
	    (match_operand:HI 1 "nonimmediate_operand" "dAmu,dA,dA,m,!u,m,!u")))
   (clobber (match_scratch:HI 2 "=X,X,X,&d,&dB,&dB,&dB"))]
  ""
  "#")

(define_split
  [(set (match_operand:SI 0 "non_push_operand" "")
	(zero_extend:SI 
	    (match_operand:HI 1 "nonimmediate_operand" "")))
   (clobber (match_scratch:HI 2 ""))]
  "reload_completed"
  [(const_int 0)]
  "
{
  rtx src = operands[1];

  if (!H_REG_P (src) && !H_REG_P (operands[0]))
    {
      src = operands[2];
      emit_move_insn (src, operands[1]);
    }
  emit_move_insn (m68hc11_gen_lowpart (HImode, operands[0]), src);
  emit_move_insn (m68hc11_gen_highpart (HImode, operands[0]), const0_rtx);
  DONE;
}")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "non_push_operand" "=D,D,m,m,u")
      (zero_extend:SI 
	  (match_operand:QI 1 "nonimmediate_operand" "dmu,xy,d,xy,dxy")))]
  ""
  "#")

(define_split 
  [(set (match_operand:SI 0 "non_push_operand" "")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  "reload_completed && !X_REG_P (operands[0])"
  [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
   (set (match_dup 3) (const_int 0))]
  "
   operands[2] = m68hc11_gen_lowpart (HImode, operands[0]);
   operands[3] = m68hc11_gen_highpart (HImode, operands[0]);")

(define_split 
  [(set (match_operand:SI 0 "hard_reg_operand" "")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  "z_replacement_completed == 2 && X_REG_P (operands[0])"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (const_int 0))
   (set (match_dup 5) (zero_extend:HI (match_dup 6)))]
  "
   if (X_REG_P (operands[1]))
     {
	emit_insn (gen_swap_areg (gen_rtx (REG, HImode, HARD_D_REGNUM),
				  gen_rtx (REG, HImode, HARD_X_REGNUM)));
	emit_insn (gen_zero_extendqihi2 (gen_rtx (REG, HImode, HARD_D_REGNUM),
					 gen_rtx (REG, QImode, HARD_D_REGNUM)));
	emit_move_insn (gen_rtx (REG, HImode, HARD_X_REGNUM),
			const0_rtx);
	DONE;
     }