mcore.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

;; Conditional branch insns

;; At top-level, condition test are eq/ne, because we
;; are comparing against the condition register (which
;; has the result of the true relational test

; There is no beq compare, so we reverse the branch arms.

(define_expand "beq"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (EQ);
}")

(define_expand "bne"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (NE);
}")

; check whether (GT A imm) can become (LE A imm) with the branch reversed.  
; if so, emit a (LT A imm + 1) in place of the (LE A imm).  BRC

(define_expand "bgt"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_jump_insn (gen_reverse_blt (operands[0]));
      DONE;
    }
  operands[1] = mcore_gen_compare_reg (GT);
}")

; There is no ble compare, so we reverse the branch arms.
; reversed the condition and branch arms for ble -- the check_dbra_loop()
; transformation assumes that ble uses a branch-true with the label as
; as the target. BRC

; check whether (LE A imm) can become (LT A imm + 1).

(define_expand "ble"
  [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
                           (pc)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_jump_insn (gen_blt (operands[0]));
      DONE;
    }
  operands[1] = mcore_gen_compare_reg (LE);
}")

; make generating a reversed blt simple
(define_expand "reverse_blt"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
                           (pc)
                           (label_ref (match_operand 0 "" ""))))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

(define_expand "blt"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

; There is no bge compare, so we reverse the branch arms.

(define_expand "bge"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (GE);
}")

; There is no gtu compare, so we reverse the branch arms

;(define_expand "bgtu"
;  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
;			   (pc)
;			   (label_ref (match_operand 0 "" ""))))]
;  ""
;  "
;{
;  if (GET_CODE (arch_compare_op1) == CONST_INT
;      && INTVAL (arch_compare_op1) == 0)
;    operands[1] = mcore_gen_compare_reg (NE);
;  else 
;    { if (mcore_modify_comparison (GTU))
;	{
;	  emit_jump_insn (gen_bgeu (operands[0]));
;	  DONE;
;	}
;      operands[1] = mcore_gen_compare_reg (LEU);
;    }
;}")

(define_expand "bgtu"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "
{
  if (GET_CODE (arch_compare_op1) == CONST_INT
      && INTVAL (arch_compare_op1) == 0)
    {
      /* The inverse of '> 0' for an unsigned test is
	 '== 0' but we do not have such an instruction available.
	 Instead we must reverse the branch (back to the normal
	 ordering) and test '!= 0'.  */
	 
      operands[1] = mcore_gen_compare_reg (NE);
      
      emit_jump_insn (gen_rtx_SET (VOIDmode,
	pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_NE (VOIDmode,
	operands[1],
	const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,operands[0]),
	pc_rtx)));
      DONE;	      
    }
  operands[1] = mcore_gen_compare_reg (GTU);
}")


(define_expand "bleu"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LEU);
}")

; There is no bltu compare, so we reverse the branch arms
(define_expand "bltu"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LTU);
}")

(define_expand "bgeu"
  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "
{

  operands[1] = mcore_gen_compare_reg (GEU);
}")

;; ------------------------------------------------------------------------
;; Jump and linkage insns
;; ------------------------------------------------------------------------

(define_insn "jump_real"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jbr	%l0"
  [(set_attr "type" "branch")])

(define_expand "jump"
 [(set (pc) (label_ref (match_operand 0 "" "")))]
 ""
 "
{
  emit_jump_insn (gen_jump_real (operand0));
  DONE;
}
")

(define_insn "indirect_jump"
  [(set (pc)
	(match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
  ""
  "jmp	%0"
  [(set_attr "type" "jmp")])

(define_expand "call"
  [(parallel[(call (match_operand:SI 0 "" "")
		   (match_operand 1 "" ""))
	     (clobber (reg:SI 15))])]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! register_operand (XEXP (operands[0], 0), SImode)
      && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
    operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
			   force_reg (Pmode, XEXP (operands[0], 0)));
}")

(define_insn "call_internal"
  [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
	 (match_operand 1 "" ""))
   (clobber (reg:SI 15))]
  ""
  "* return mcore_output_call (operands, 0);")

(define_expand "call_value"
  [(parallel[(set (match_operand 0 "register_operand" "")
		  (call (match_operand:SI 1 "" "")
			(match_operand 2 "" "")))
	     (clobber (reg:SI 15))])]
  ""
  "
{
  if (GET_CODE (operands[0]) == MEM
      && ! register_operand (XEXP (operands[0], 0), SImode)
      && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
    operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
			   force_reg (Pmode, XEXP (operands[1], 0)));
}")

(define_insn "call_value_internal"
  [(set (match_operand 0 "register_operand" "=r")
	(call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
	      (match_operand 2 "" "")))
   (clobber (reg:SI 15))]
  ""
  "* return mcore_output_call (operands, 1);")

(define_insn "call_value_struct"
  [(parallel [(set (match_parallel 0 ""
	             [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
		      (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
		  (call (match_operand:SI 1 "" "")
			(match_operand 2 "" "")))
	     (clobber (reg:SI 15))])]
  ""
  "* return mcore_output_call (operands, 1);"
)


;; ------------------------------------------------------------------------
;; Misc insns
;; ------------------------------------------------------------------------

(define_insn "nop"
  [(const_int 0)]
  ""
  "or	r0,r0")

(define_insn "tablejump"
  [(set (pc)
	(match_operand:SI 0 "mcore_arith_reg_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp	%0"
  [(set_attr "type" "jmp")])

(define_insn "*return"
 [(return)]
 "reload_completed && ! mcore_naked_function_p ()"
 "jmp	r15"
 [(set_attr "type" "jmp")])

(define_insn "*no_return"
 [(return)]
 "reload_completed && mcore_naked_function_p ()"
 ""
 [(set_attr "length" "0")]
)

(define_expand "prologue"
  [(const_int 0)]
  ""
  "mcore_expand_prolog (); DONE;")

(define_expand "epilogue"
  [(return)]
  ""
  "mcore_expand_epilog ();")

;; ------------------------------------------------------------------------
;; Scc instructions
;; ------------------------------------------------------------------------

(define_insn "mvc"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(ne:SI (reg:CC 17) (const_int 0)))]
  ""
  "mvc	%0"
  [(set_attr "type" "move")])

(define_insn "mvcv"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
	(eq:SI (reg:CC 17) (const_int 0)))]
  ""
  "mvcv	%0"
  [(set_attr "type" "move")])

; in 0.97 use (LE 0) with (LT 1) and complement c.  BRC
(define_split 
  [(parallel[
     (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
          (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
                        (const_int 0))
                 (const_int 0)))
     (clobber (reg:SI 17))])]
  ""
  [(set (reg:CC 17)
        (lt:CC (match_dup 1) (const_int 1)))
   (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
     

(define_expand "seq"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (NE);
}")

(define_expand "sne"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (NE);
}")

(define_expand "slt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

; make generating a LT with the comparison reversed easy.  BRC
(define_expand "reverse_slt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
        (eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

(define_expand "sge"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  operands[1] = mcore_gen_compare_reg (LT);
}")

; check whether (GT A imm) can become (LE A imm) with the comparison
; reversed.  if so, emit a (LT A imm + 1) in place of the (LE A imm).  BRC

(define_expand "sgt"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_insn (gen_reverse_slt (operands[0]));
      DONE;
    }
  
  operands[1] = mcore_gen_compare_reg (GT);
}")

(define_expand "sle"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_int 0)))]
  ""
  "
{
  if (mcore_modify_comparison (LE))
    {
      emit_insn (gen_slt (operands[0]));
      DONE;
    }
  operands[1] = mcore_gen_compare_reg (GT);
}")

(define_expand "sltu"
  [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
	(eq:SI (match_dup 1) (const_i