xtensa.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

}"
  [(set_attr "type"	"move,load,store,move,load,load,store")
   (set_attr "mode"	"DI")
   (set_attr "length"	"4,4,4,6,6,6,6")])


;; 32-bit Integer moves

(define_expand "movsi"
  [(set (match_operand:SI 0 "nonimmed_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "
{
  if (xtensa_emit_move_sequence (operands, SImode))
    DONE;
}")

(define_insn "movsi_internal"
  [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,a,a,U,*a,*A")
	(match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,T,U,r,*A,*r"))]
  "xtensa_valid_move (SImode, operands)"
  "@
   movi.n\\t%0, %x1
   mov.n\\t%0, %1
   mov.n\\t%0, %1
   %v1l32i.n\\t%0, %1
   %v0s32i.n\\t%1, %0
   %v0s32i.n\\t%1, %0
   mov\\t%0, %1
   movsp\\t%0, %1
   movi\\t%0, %x1
   %v1l32r\\t%0, %1
   %v1l32i\\t%0, %1
   %v0s32i\\t%1, %0
   rsr\\t%0, 16 # ACCLO
   wsr\\t%1, 16 # ACCLO"
  [(set_attr "type"	"move,move,move,load,store,store,move,move,move,load,load,store,rsr,wsr")
   (set_attr "mode"	"SI")
   (set_attr "length"	"2,2,2,2,2,2,3,3,3,3,3,3,3,3")])

;; 16-bit Integer moves

(define_expand "movhi"
  [(set (match_operand:HI 0 "nonimmed_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "
{
  if (xtensa_emit_move_sequence (operands, HImode))
    DONE;
}")

(define_insn "movhi_internal"
  [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
	(match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
  "xtensa_valid_move (HImode, operands)"
  "@
   movi.n\\t%0, %x1
   mov.n\\t%0, %1
   mov\\t%0, %1
   movi\\t%0, %x1
   %v1l16ui\\t%0, %1
   %v0s16i\\t%1, %0
   rsr\\t%0, 16 # ACCLO
   wsr\\t%1, 16 # ACCLO"
  [(set_attr "type"	"move,move,move,move,load,store,rsr,wsr")
   (set_attr "mode"	"HI")
   (set_attr "length"	"2,2,3,3,3,3,3,3")])

;; 8-bit Integer moves

(define_expand "movqi"
  [(set (match_operand:QI 0 "nonimmed_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  "
{
  if (xtensa_emit_move_sequence (operands, QImode))
    DONE;
}")

(define_insn "movqi_internal"
  [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
	(match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
  "xtensa_valid_move (QImode, operands)"
  "@
   movi.n\\t%0, %x1
   mov.n\\t%0, %1
   mov\\t%0, %1
   movi\\t%0, %x1
   %v1l8ui\\t%0, %1
   %v0s8i\\t%1, %0
   rsr\\t%0, 16 # ACCLO
   wsr\\t%1, 16 # ACCLO"
  [(set_attr "type"	"move,move,move,move,load,store,rsr,wsr")
   (set_attr "mode"	"QI")
   (set_attr "length"	"2,2,3,3,3,3,3,3")])

;; 32-bit floating point moves

(define_expand "movsf"
  [(set (match_operand:SF 0 "nonimmed_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    operands[1] = force_const_mem (SFmode, operands[1]);

  if (!(reload_in_progress | reload_completed))
    {
      if (((!register_operand (operands[0], SFmode)
	   && !register_operand (operands[1], SFmode))
	  || (FP_REG_P (xt_true_regnum (operands[0]))
	      && constantpool_mem_p (operands[1]))))
	operands[1] = force_reg (SFmode, operands[1]);

      if (xtensa_copy_incoming_a7 (operands, SFmode))
	DONE;
    }
}")

(define_insn "movsf_internal"
  [(set (match_operand:SF 0 "nonimmed_operand"
			    "=f,f,U,D,D,R,a,f,a,a,a,U")
	(match_operand:SF 1 "non_const_move_operand"
			    "f,U,f,d,R,d,r,r,f,T,U,r"))]
  "((register_operand (operands[0], SFmode)
     || register_operand (operands[1], SFmode))
    && (!FP_REG_P (xt_true_regnum (operands[0]))
        || !constantpool_mem_p (operands[1])))"
  "@
   mov.s\\t%0, %1
   %v1lsi\\t%0, %1
   %v0ssi\\t%1, %0
   mov.n\\t%0, %1
   %v1l32i.n\\t%0, %1
   %v0s32i.n\\t%1, %0
   mov\\t%0, %1
   wfr\\t%0, %1
   rfr\\t%0, %1
   %v1l32r\\t%0, %1
   %v1l32i\\t%0, %1
   %v0s32i\\t%1, %0"
  [(set_attr "type"	"farith,fload,fstore,move,load,store,move,farith,farith,load,load,store")
   (set_attr "mode"	"SF")
   (set_attr "length"	"3,3,3,2,2,2,3,3,3,3,3,3")])

(define_insn "*lsiu"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "+a")
			 (match_operand:SI 2 "fpmem_offset_operand" "i"))))
   (set (match_dup 1)
	(plus:SI (match_dup 1) (match_dup 2)))]
  "TARGET_HARD_FLOAT"
  "*
{
  if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
    output_asm_insn (\"memw\", operands);
  return \"lsiu\\t%0, %1, %2\";
}"
  [(set_attr "type"	"fload")
   (set_attr "mode"	"SF")
   (set_attr "length"	"3")])

(define_insn "*ssiu"
  [(set (mem:SF (plus:SI (match_operand:SI 0 "register_operand" "+a")
			 (match_operand:SI 1 "fpmem_offset_operand" "i")))
	(match_operand:SF 2 "register_operand" "f"))
   (set (match_dup 0)
	(plus:SI (match_dup 0) (match_dup 1)))]
  "TARGET_HARD_FLOAT"
  "*
{
  if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
    output_asm_insn (\"memw\", operands);
  return \"ssiu\\t%2, %0, %1\";
}"
  [(set_attr "type"	"fstore")
   (set_attr "mode"	"SF")
   (set_attr "length"	"3")])

;; 64-bit floating point moves

(define_expand "movdf"
  [(set (match_operand:DF 0 "nonimmed_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
  "
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    operands[1] = force_const_mem (DFmode, operands[1]);

  if (!(reload_in_progress | reload_completed))
    {
      if (!register_operand (operands[0], DFmode)
	  && !register_operand (operands[1], DFmode))
	operands[1] = force_reg (DFmode, operands[1]);

      if (xtensa_copy_incoming_a7 (operands, DFmode))
	DONE;
    }
}")

(define_insn "movdf_internal"
  [(set (match_operand:DF 0 "nonimmed_operand" "=D,D,S,a,a,a,U")
	(match_operand:DF 1 "non_const_move_operand" "d,S,d,r,T,U,r"))]
  "register_operand (operands[0], DFmode)
   || register_operand (operands[1], DFmode)"
  "*
{
  switch (which_alternative)
    {
    case 0: return \"mov.n\\t%0, %1\;mov.n\\t%D0, %D1\";
    case 2: return \"%v0s32i.n\\t%1, %0\;s32i.n\\t%D1, %N0\";
    case 3: return \"mov\\t%0, %1\;mov\\t%D0, %D1\";
    case 6: return \"%v0s32i\\t%1, %0\;s32i\\t%D1, %N0\";

    case 1:
    case 4:
    case 5:
      {
	/* Check if the first half of the destination register is used
	   in the source address.  If so, reverse the order of the loads
	   so that the source address doesn't get clobbered until it is
	   no longer needed. */

	rtx dstreg = operands[0];
	if (GET_CODE (dstreg) == SUBREG)
	  dstreg = SUBREG_REG (dstreg);
	if (GET_CODE (dstreg) != REG)
	  abort ();

	if (reg_mentioned_p (dstreg, operands[1]))
	  {
	    switch (which_alternative)
	      {
	      case 1: return \"%v1l32i.n\\t%D0, %N1\;l32i.n\\t%0, %1\";
	      case 4: return \"%v1l32r\\t%D0, %N1\;l32r\\t%0, %1\";
	      case 5: return \"%v1l32i\\t%D0, %N1\;l32i\\t%0, %1\";
	      }
	  }
	else
	  {
	    switch (which_alternative)
	      {
	      case 1: return \"%v1l32i.n\\t%0, %1\;l32i.n\\t%D0, %N1\";
	      case 4: return \"%v1l32r\\t%0, %1\;l32r\\t%D0, %N1\";
	      case 5: return \"%v1l32i\\t%0, %1\;l32i\\t%D0, %N1\";
	      }
	  }
      }
    }
  abort ();
  return \"\";
}"
  [(set_attr "type"	"move,load,store,move,load,load,store")
   (set_attr "mode"	"DF")
   (set_attr "length"	"4,4,4,6,6,6,6")])

;; Block moves

(define_expand "movstrsi"
  [(parallel [(set (match_operand:BLK 0 "" "")
		   (match_operand:BLK 1 "" ""))
	      (use (match_operand:SI 2 "arith_operand" ""))
	      (use (match_operand:SI 3 "const_int_operand" ""))])]
  ""
  "
{
  if (!xtensa_expand_block_move (operands)) FAIL;
  DONE;
}")

(define_insn "movstrsi_internal"
  [(set (match_operand:BLK 0 "memory_operand" "=U")
	(match_operand:BLK 1 "memory_operand" "U"))
   (use (match_operand:SI 2 "arith_operand" ""))
   (use (match_operand:SI 3 "const_int_operand" ""))
   (clobber (match_scratch:SI 4 "=&r"))
   (clobber (match_scratch:SI 5 "=&r"))]
  ""
  "*
{
  rtx tmpregs[2];
  tmpregs[0] = operands[4];
  tmpregs[1] = operands[5];
  xtensa_emit_block_move (operands, tmpregs, 1);
  return \"\";
}"
  [(set_attr "type"	"multi")
   (set_attr "mode"	"none")
   (set_attr "length"	"300")])


;;
;;  ....................
;;
;;	SHIFTS
;;
;;  ....................
;;

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,a")
	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
		   (match_operand:SI 2 "arith_operand" "J,r")))]
  ""      
  "@
   slli\\t%0, %1, %R2
   ssl\\t%2\;sll\\t%0, %1"
  [(set_attr "type"	"arith,arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"3,6")])

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,a")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
		     (match_operand:SI 2 "arith_operand" "J,r")))]
  ""
  "@
   srai\\t%0, %1, %R2
   ssr\\t%2\;sra\\t%0, %1"
  [(set_attr "type"	"arith,arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"3,6")])

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,a")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
		     (match_operand:SI 2 "arith_operand" "J,r")))]
  ""
  "*
{
  if (which_alternative == 0)
    {
      if ((INTVAL (operands[2]) & 0x1f) < 16)
        return \"srli\\t%0, %1, %R2\";
      else
      	return \"extui\\t%0, %1, %R2, %L2\";
    }
  return \"ssr\\t%2\;srl\\t%0, %1\";
}"
  [(set_attr "type"	"arith,arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"3,6")])

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,a")
	(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
		     (match_operand:SI 2 "arith_operand" "J,r")))]
  ""
  "@
   ssai\\t%L2\;src\\t%0, %1, %1
   ssl\\t%2\;src\\t%0, %1, %1"
  [(set_attr "type"	"multi,multi")
   (set_attr "mode"	"SI")
   (set_attr "length"	"6,6")])

(define_insn "rotrsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,a")
	(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
		     (match_operand:SI 2 "arith_operand" "J,r")))]
  ""
  "@
   ssai\\t%R2\;src\\t%0, %1, %1
   ssr\\t%2\;src\\t%0, %1, %1"
  [(set_attr "type"	"multi,multi")
   (set_attr "mode"	"SI")
   (set_attr "length"	"6,6")])


;;
;;  ....................
;;
;;	COMPARISONS
;;
;;  ....................
;;

;; Like the md files for MIPS and SPARC, we handle comparisons by stashing
;; away the operands and then using that information in the subsequent
;; conditional branch.

(define_expand "cmpsi"
  [(set (cc0)
	(compare:CC (match_operand:SI 0 "register_operand" "")
		    (match_operand:SI 1 "nonmemory_operand" "")))]
  ""
  "
{
  branch_cmp[0] = operands[0];
  branch_cmp[1] = operands[1];
  branch_type = CMP_SI;
  DONE;
}")

(define_expand "tstsi"
  [(set (cc0)
	(match_operand:SI 0 "register_operand" ""))]
  ""
  "
{
  branch_cmp[0] = operands[0];
  branch_cmp[1] = const0_rtx;
  branch_type = CMP_SI;
  DONE;
}")

(define_expand "cmpsf"
  [(set (cc0)
	(compare:CC (match_operand:SF 0 "register_operand" "")
		    (match_operand:SF 1 "register_operand" "")))]
  "TARGET_HARD_FLOAT"
  "
{
  branch_cmp[0] = operands[0];
  branch_cmp[1] = operands[1];
  branch_type = CMP_SF;
  DONE;
}")


;;
;;  ....................
;;
;;	CONDITIONAL BRANCHES
;;
;;  ....................
;;

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  xtensa_expand_conditional_branch (operands, EQ);
  DONE;
}")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  xtensa_expand_conditional_branch (operands, NE);
  DONE;
}")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  xtensa_expand_conditional_branch (operands, GT);
  DONE;
}")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  xtensa_expand_conditional_branch (operands, GE);
  DONE;
}")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  xtensa_expand_conditional_branch (operands, LT);
  DONE;
}")

(define_expand "ble"
  [(set (pc)
	(if_then_else (le (cc0) (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{