d30v.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

	      (clobber (match_dup 2))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  "
{
  operands[2] = gen_rtx (REG, CCmode, FLAG_CARRY);
  operands[3] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
  operands[4] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
}")

(define_insn "*negdi2_internal"
  [(set (match_operand:DI 0 "gpr_operand" "=e")
	(neg:DI (match_operand:DI 1 "gpr_operand" "e")))
   (clobber (match_operand:CC 2 "flag_operand" "=f"))
   (clobber (match_operand:CC 3 "flag_operand" "=f"))
   (clobber (match_operand:CC 4 "flag_operand" "=f"))]
  ""
  "#"
  [(set_attr "length" "8")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "=e")
	(neg:DI (match_operand:DI 1 "gpr_operand" "e")))
   (clobber (match_operand:CC 2 "flag_operand" "=f"))
   (clobber (match_operand:CC 3 "flag_operand" "=f"))
   (clobber (match_operand:CC 4 "flag_operand" "=f"))]
  "reload_completed"
  [(match_dup 5)
   (match_dup 6)]
  "
{
  rtx high[2];
  rtx low[2];
  rtx r0 = const0_rtx;

  d30v_split_double (operands[0], &high[0], &low[0]);
  d30v_split_double (operands[1], &high[1], &low[1]);

  operands[5] = gen_subsi3_set_carry (low[0], r0, low[1], operands[2],
				      operands[3], operands[4]);

  operands[6] = gen_subsi3_use_carry (high[0], r0, high[1], operands[2],
				      operands[3], operands[4]);
}")


;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left (negate the shift value and use shift right)
(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "gpr_operand" "")
	(ashift:SI (match_operand:SI 1 "gpr_operand" "")
		   (match_operand:SI 2 "gpr_or_unsigned5_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn "*ashlsi3_constant"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(ashift:SI (match_operand:SI 1 "gpr_operand" "d")
		   (match_operand:SI 2 "unsigned5_operand" "J")))]
  ""
  "sra%: %0,%1,%n2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])

(define_insn "*ashlsi3_register"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(ashift:SI (match_operand:SI 1 "gpr_operand" "d")
		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))]
  ""
  "sra%: %0,%1,%2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])

;; Arithmetic Shift Right
(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(ashiftrt:SI (match_operand:SI 1 "gpr_operand" "d")
		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
  ""
  "sra%: %0,%1,%2"
  [(set_attr "length" "4")])

;; Logical Shift Right
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(lshiftrt:SI (match_operand:SI 1 "gpr_operand" "d")
		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
  ""
  "srl%: %0,%1,%2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])

;; Rotate Left (negate the shift value and use rotate right)
(define_expand "rotlsi3"
  [(set (match_operand:SI 0 "gpr_operand" "")
	(rotate:SI (match_operand:SI 1 "gpr_operand" "")
		   (match_operand:SI 2 "gpr_or_unsigned5_operand" "")))]
  ""
  "
{
  if (GET_CODE (operands[2]) != CONST_INT)
    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn "*rotlsi3_constant"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(rotate:SI (match_operand:SI 1 "gpr_operand" "d")
		   (match_operand:SI 2 "unsigned5_operand" "J")))]
  ""
  "rot%: %0,%1,%n2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])

(define_insn "*rotlsi3_register"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(rotate:SI (match_operand:SI 1 "gpr_operand" "d")
		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))]
  ""
  "rot%: %0,%1,%2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])

;; Rotate Right
(define_insn "rotrsi3"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(rotatert:SI (match_operand:SI 1 "gpr_operand" "d")
		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
  ""
  "rot%: %0,%1,%2"
  [(set_attr "length" "4")
   (set_attr "type" "either")])


;; ::::::::::::::::::::
;; ::
;; :: 64 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left
(define_expand "ashldi3"
  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
		   (ashift:DI (match_operand:DI 1 "gpr_operand" "")
			      (match_operand:SI 2 "gpr_or_unsigned6_operand" "")))
	      (clobber (match_scratch:CC 3 ""))])]
  ""
  "
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (IN_RANGE_P (INTVAL (operands[2]), 0, 63))
	{
	  emit_insn (gen_ashldi3_constant (operands[0], operands[1], operands[2]));
	  DONE;
	}
      else
	operands[2] = copy_to_mode_reg (SImode, operands[2]);
    }

  operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
}")

(define_insn "ashldi3_constant"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e")
	(ashift:DI (match_operand:DI 1 "gpr_operand" "0,e")
		   (match_operand:SI 2 "unsigned6_operand" "J,P")))]
  ""
  "@
    src%: %U0,%L0,%n2\;sra%: %L0,%L0,%n2
    sra%: %U0,%L1,%s2\;or%: %L0,%.,0"
  [(set_attr "length" "8")
   (set_attr "type" "multi")])

(define_insn "*ashldi3_register"
  [(set (match_operand:DI 0 "gpr_operand" "=e")
	(ashift:DI (match_operand:DI 1 "gpr_operand" "0")
		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))
   (clobber (match_scratch:CC 3 "=b"))]
  ""
  "cmpge %3,%2,-31\;src%T3 %U0,%L0,%2\;sra%T3 %L0,%L0,%2\;sub%F3 %U0,%2,-32\;sra%F3 %U0,%L0,%U0\;or%F3 %L0,%.,0"
  [(set_attr "length" "32")
   (set_attr "type" "multi")
   ;; Not strictly true, since we ought to be able to combine conditions,
   (set_attr "predicable" "no")])

;; Arithmetic Shift Right
(define_insn "ashrdi3"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(ashiftrt:DI (match_operand:DI 1 "gpr_operand" "0,e,0")
		     (match_operand:SI 2 "gpr_or_unsigned6_operand" "J,P,d")))
   (clobber (match_scratch:CC 3 "=X,X,b"))]
  ""
  "@
    src %L0,%U0,%2\;sra %U0,%U0,%2
    sra %L0,%U1,%S2\;sra %U0,%L0,31
    cmple %3,%2,31\;src%T3 %L0,%U0,%2\;sra%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;sra%F3 %L0,%U0,%L0\;sra%F3 %U0,%U0,31"
  [(set_attr "length" "8,8,28")
   (set_attr "type" "multi")
   ;; Not strictly true, since we ought to be able to combine conditions,
   (set_attr "predicable" "no")])

;; Logical Shift Right

(define_insn "lshrdi3"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(lshiftrt:DI (match_operand:DI 1 "gpr_operand" "0,e,0")
		     (match_operand:SI 2 "gpr_or_unsigned6_operand" "J,P,d")))
   (clobber (match_scratch:CC 3 "=X,X,b"))]
  ""
  "@
    src %L0,%U0,%2\;srl %U0,%U0,%2
    srl %L0,%U1,%S2\;or %U0,%.,0
    cmple %3,%2,31\;src%T3 %L0,%U0,%2\;srl%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;srl%F3 %L0,%U0,%L0\;or%F3 %U0,%.,0"
  [(set_attr "length" "8,8,28")
   (set_attr "type" "multi")
   ;; Not strictly true, since we ought to be able to combine conditions,
   (set_attr "predicable" "no")])


;; ::::::::::::::::::::
;; ::
;; :: 32 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::

;; Logical AND, 32 bit integers

(define_insn "andsi3"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
	(and:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d")
		(match_operand:SI 2 "gpr_or_constant_operand" "L,I,i,d")))]
  ""
  "@
    bclr%: %0,%1,%B2
    and%: %0,%1,%2
    and%: %0,%1,%2
    and%: %0,%1,%2"
  [(set_attr "length" "4,4,8,4")
   (set_attr "type" "either,either,long,either")])

;; Inclusive OR, 32 bit integers

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
	(ior:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d")
		(match_operand:SI 2 "gpr_or_constant_operand" "K,I,i,d")))]
  ""
  "@
    bset%: %0,%1,%B2
    or%: %0,%1,%2
    or%: %0,%1,%2
    or%: %0,%1,%2"
  [(set_attr "length" "4,4,8,4")
   (set_attr "type" "either,either,long,either")])

;; Exclusive OR, 32 bit integers

(define_insn "*xorsi3_constant"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
	(xor:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d")
		(match_operand:SI 2 "gpr_or_constant_operand" "K,I,i,d")))]
  ""
  "@
    bnot%: %0,%1,%B2
    xor%: %0,%1,%2
    xor%: %0,%1,%2
    xor%: %0,%1,%2"
  [(set_attr "length" "4,4,8,4")
   (set_attr "type" "either,either,long,either")])

;; One's complement, 32 bit integers
(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "gpr_operand" "=d")
	(not:SI (match_operand:SI 1 "gpr_operand" "d")))]
  ""
  "not%: %0,%1"
  [(set_attr "length" "4")
   (set_attr "type" "either")])


;; ::::::::::::::::::::
;; ::
;; :: 64 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::

;; Logical AND, 64 bit integers
(define_insn "anddi3"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
	(and:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
  ""
  "#"
  [(set_attr "length" "8,8,8,8,12,16")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(and:DI (match_operand:DI 1 "gpr_operand" "")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
  "reload_completed"
  [(set (match_dup 3) (and:SI (match_dup 4) (match_dup 5)))
   (set (match_dup 6) (and:SI (match_dup 7) (match_dup 8)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[6]);
  d30v_split_double (operands[1], &operands[4], &operands[7]);
  d30v_split_double (operands[2], &operands[5], &operands[8]);
}")

;; Includive OR, 64 bit integers
(define_insn "iordi3"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
	(ior:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
  ""
  "#"
  [(set_attr "length" "8,8,8,8,12,16")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(ior:DI (match_operand:DI 1 "gpr_operand" "")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
  "reload_completed"
  [(set (match_dup 3) (ior:SI (match_dup 4) (match_dup 5)))
   (set (match_dup 6) (ior:SI (match_dup 7) (match_dup 8)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[6]);
  d30v_split_double (operands[1], &operands[4], &operands[7]);
  d30v_split_double (operands[2], &operands[5], &operands[8]);
}")

;; Excludive OR, 64 bit integers
(define_insn "xordi3"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
	(xor:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
  ""
  "#"
  [(set_attr "length" "8,8,8,8,12,16")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(xor:DI (match_operand:DI 1 "gpr_operand" "")
		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
  "reload_completed"
  [(set (match_dup 3) (xor:SI (match_dup 4) (match_dup 5)))
   (set (match_dup 6) (xor:SI (match_dup 7) (match_dup 8)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[6]);
  d30v_split_double (operands[1], &operands[4], &operands[7]);
  d30v_split_double (operands[2], &operands[5], &operands[8]);
}")

;; One's complement, 64 bit integers
(define_insn "one_cmpldi2"
  [(set