d30v.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

  else if (GET_CODE (operands[1]) == MINUS)
    {
      emit_insn (gen_subsi3 (operands[0], XEXP (operands[1], 0),
			     XEXP (operands[1], 1)));
      DONE;
    }
}")

(define_insn "*movsi_internal"
  [(set (match_operand:SI 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m,d,c")
	(match_operand:SI 1 "move_input_operand" "dI,F,i,Q,m,d,d,O,O,c,d"))]
  "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
  "@
    or%: %0,%.,%1
    or%: %0,%.,%L1
    or%: %0,%.,%1
    ldw%: %0,%M1
    ldw%: %0,%M1
    stw%: %1,%M0
    stw%: %1,%M0
    stw%: %.,%M0
    stw%: %.,%M0
    mvfsys%: %0,%1
    mvtsys%: %0,%1"
  [(set_attr "length" "4,8,8,4,8,4,8,4,8,4,4")
   (set_attr "type" "either,long,long,sload,lload,mu,long,mu,long,mu,mu")])

(define_expand "movdi"
  [(set (match_operand:DI 0 "general_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress && !reload_completed
      && !register_operand (operands[0], DImode)
      && !register_operand (operands[1], DImode))
    operands[1] = copy_to_mode_reg (DImode, operands[1]);
}")

(define_insn "*movdi_internal"
  [(set (match_operand:DI 0 "move_output_operand" "=e,e,e,e,Q,m,e,a,a")
	(match_operand:DI 1 "move_input_operand" "eI,iF,Q,m,e,e,a,e,O"))]
  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
  "* return d30v_move_2words (operands, insn);"
  [(set_attr "length" "8,16,4,8,4,8,8,4,4")
   (set_attr "type" "multi,multi,sload,lload,mu,long,multi,iu,iu")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(match_operand:DI 1 "gpr_or_dbl_const_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "
{
  d30v_split_double (operands[0], &operands[2], &operands[4]);
  d30v_split_double (operands[1], &operands[3], &operands[5]);
}")

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
	(match_operand:SF 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress && !reload_completed
      && !register_operand (operands[0], SFmode)
      && !reg_or_0_operand (operands[1], SFmode))
    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
}")

(define_insn "*movsf_internal"
  [(set (match_operand:SF 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m")
	(match_operand:SF 1 "move_input_operand" "d,G,F,Q,m,d,d,G,G"))]
  "register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)"
  "@
    or%: %0,%.,%1
    or%: %0,%.,0
    or%: %0,%.,%f1
    ldw%: %0,%M1
    ldw%: %0,%M1
    stw%: %1,%M0
    stw%: %1,%M0
    stw%: %.,%M0
    stw%: %.,%M0"
  [(set_attr "length" "4,4,8,4,8,4,8,4,8")
   (set_attr "type" "either,either,long,sload,lload,mu,long,mu,long")])

(define_expand "movdf"
  [(set (match_operand:DF 0 "general_operand" "")
	(match_operand:DF 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress && !reload_completed
      && !register_operand (operands[0], DFmode)
      && !register_operand (operands[1], DFmode))
    operands[1] = copy_to_mode_reg (DFmode, operands[1]);
}")

(define_insn "*movdf_internal"
  [(set (match_operand:DF 0 "move_output_operand" "=e,e,e,e,Q,m,!*e,!*a")
	(match_operand:DF 1 "move_input_operand" "eG,F,Q,m,e,e,!*a,!*e"))]
  "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
  "* return d30v_move_2words (operands, insn);"
  [(set_attr "length" "8,16,4,8,4,8,8,4")
   (set_attr "type" "multi,multi,sload,lload,mu,long,multi,iu")])

(define_split
  [(set (match_operand:DF 0 "gpr_operand" "")
	(match_operand:DF 1 "gpr_or_dbl_const_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "
{
  d30v_split_double (operands[0], &operands[2], &operands[4]);
  d30v_split_double (operands[1], &operands[3], &operands[5]);
}")

(define_expand "movcc"
  [(set (match_operand:CC 0 "general_operand" "")
	(match_operand:CC 1 "general_operand" ""))]
  ""
  "
{
  if (!reload_in_progress && !reload_completed
      && GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM)
    operands[1] = copy_to_mode_reg (CCmode, operands[1]);
}")

(define_insn "*movcc_internal"
  [(set (match_operand:CC 0 "move_output_operand" "=f,f,f,d,?d,f,d,*d,*d,*Q,*m")
	(match_operand:CC 1 "move_input_operand" "f,O,N,b,f,d,dON,*Q,*m,*d,*d"))]
  "!memory_operand (operands[0], CCmode) || !memory_operand (operands[1], CCmode)"
  "@
    orfg%: %0,%1,%1
    andfg%: %0,%0,0
    orfg%: %0,%0,1
    #
    mvfsys%: %0,%1
    cmpne%: %0,%1,0
    or%: %0,%.,%1
    ldb%: %0,%M1
    ldb%: %0,%M1
    stb%: %1,%M0
    stb%: %1,%M0"
  [(set_attr "length" "4,4,4,8,4,4,4,4,8,4,8")
   (set_attr "type" "either,either,either,multi,mu,mu,either,sload,lload,mu,long")])

(define_split
  [(set (match_operand:CC 0 "gpr_operand" "")
	(match_operand:CC 1 "br_flag_operand" ""))]
  "reload_completed"
  [(set (match_dup 2)
	(const_int 0))
   (set (match_dup 2)
	(if_then_else:SI (ne:CC (match_dup 1)
				(const_int 0))
			 (const_int 1)
			 (match_dup 2)))]
  "
{
  operands[2] = gen_lowpart (SImode, operands[0]);
}")


;; ::::::::::::::::::::
;; ::
;; :: Conversions
;; ::
;; ::::::::::::::::::::

;; Signed conversions from a smaller integer to a larger integer
(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
	(sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    #
    ldb%: %0,%M1
    ldb%: %0,%M1"
  [(set_attr "type" "multi,sload,lload")
   (set_attr "length" "16,4,8")])

(define_split
  [(set (match_operand:HI 0 "gpr_operand" "")
	(sign_extend:HI (match_operand:QI 1 "gpr_operand" "")))]
  "reload_completed"
  [(match_dup 2)
   (match_dup 3)]
  "
{
  rtx op0   = gen_lowpart (SImode, operands[0]);
  rtx op1   = gen_lowpart (SImode, operands[1]);
  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);

  operands[2] = gen_ashlsi3 (op0, op1, shift);
  operands[3] = gen_ashrsi3 (op0, op0, shift);
}")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
	(sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    #
    ldb%: %0,%M1
    ldb%: %0,%M1"
  [(set_attr "type" "multi,sload,lload")
   (set_attr "length" "16,4,8")])

(define_split
  [(set (match_operand:SI 0 "gpr_operand" "")
	(sign_extend:SI (match_operand:QI 1 "gpr_operand" "")))]
  "reload_completed"
  [(match_dup 2)
   (match_dup 3)]
  "
{
  rtx op0   = gen_lowpart (SImode, operands[0]);
  rtx op1   = gen_lowpart (SImode, operands[1]);
  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);

  operands[2] = gen_ashlsi3 (op0, op1, shift);
  operands[3] = gen_ashrsi3 (op0, op0, shift);
}")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
	(sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    #
    ldh%: %0,%M1
    ldh%: %0,%M1"
  [(set_attr "type" "multi,sload,lload")
   (set_attr "length" "16,4,8")])

(define_split
  [(set (match_operand:SI 0 "gpr_operand" "")
	(sign_extend:SI (match_operand:HI 1 "gpr_operand" "")))]
  "reload_completed"
  [(match_dup 2)
   (match_dup 3)]
  "
{
  rtx op0   = gen_lowpart (SImode, operands[0]);
  rtx op1   = gen_lowpart (SImode, operands[1]);
  rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);

  operands[2] = gen_ashlsi3 (op0, op1, shift);
  operands[3] = gen_ashrsi3 (op0, op0, shift);
}")

(define_insn "extendqidi2"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(sign_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "#"
  [(set_attr "length" "12,8,12")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(sign_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "")))]
  "reload_completed"
  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[2]);
}")

(define_insn "extendhidi2"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(sign_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "#"
  [(set_attr "length" "12,8,12")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(sign_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "")))]
  "reload_completed"
  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[2]);
}")

(define_insn "extendsidi2"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(sign_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "#"
  [(set_attr "length" "8,8,12")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(sign_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "")))]
  "reload_completed"
  [(set (match_dup 2) (match_dup 1))
   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[2]);
}")
	
;; Unsigned conversions from a smaller integer to a larger integer

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
	(zero_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    and%: %0,%1,0xff
    ldbu%: %0,%M1
    ldbu%: %0,%M1"
  [(set_attr "length" "8,4,8")
   (set_attr "type" "long,sload,lload")])

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
	(zero_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    and%: %0,%1,0xff
    ldbu%: %0,%M1
    ldbu%: %0,%M1"
  [(set_attr "length" "8,4,8")
   (set_attr "type" "long,sload,lload")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
	(zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "@
    and%: %0,%1,0xffff
    ldhu%: %0,%M1
    ldhu%: %0,%M1"
  [(set_attr "length" "8,4,8")
   (set_attr "type" "long,sload,lload")])

(define_insn "zero_extendqidi2"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(zero_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "#"
  [(set_attr "length" "12,8,12")
   (set_attr "type" "multi")])

(define_split
  [(set (match_operand:DI 0 "gpr_operand" "")
	(zero_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "")))]
  "reload_completed"
  [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
   (set (match_dup 3) (const_int 0))]
  "
{
  d30v_split_double (operands[0], &operands[3], &operands[2]);
}")

(define_insn "zero_extendhidi2"
  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
	(zero_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
  ""
  "#"
  [(set_attr "length" "8,8,12")
   (set_attr "type" "multi")])