ns32k.md

gcc-you can use this code to learn something about gcc, and inquire further into linux,

;;;; in memory. DI mode will ensure two registers are available, but if we
;;;; want to allow memory as an operand we would need SI mode. There is no
;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
;;(define_insn "udivmoddihi4_internal"
;;  [(set (match_operand:DI 0 "register_operand" "=r")
;;        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
;;                    (match_operand:HI 2 "general_operand" "g")] 0))]
;;  ""
;;  "deiw %2,%0")
;;
;;(define_insn "udivmoddihi4"
;;  [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2)
;;	(truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
;;		 (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
;;   (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
;;	(truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
;;  ""
;;  "deiw %2,%0")
;;
;;(define_expand "udivmodqi4"
;;  [(parallel
;;  [(set (match_operand:QI 0 "nonimmediate_operand" "")
;;	(udiv:QI (match_operand:QI 1 "general_operand" "")
;;		     (match_operand:QI 2 "general_operand" "")))
;;   (set (match_operand:QI 3 "nonimmediate_operand" "")
;;	(umod:QI (match_dup 1) (match_dup 2)))])]
;;  ""
;;  "
;;{
;;  rtx temp = gen_reg_rtx(DImode);
;;  rtx insn, first, last;
;;  first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
;;  emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
;;  operands[2] = force_reg(QImode, operands[2]);
;;  emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
;;  last = emit_move_insn(temp, temp);
;;  {
;;    rtx divdi, moddi, divqi, modqi;
;;    divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
;;    modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
;;    divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
;;    moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
;;    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
;;			         REG_NOTES (first));
;;    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
;;                                gen_rtx (EXPR_LIST, REG_EQUAL,
;;                       gen_rtx(IOR, DImode, moddi,
;;                               gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
;;                       REG_NOTES (last)));
;;  }
;;
;;  insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
;;  insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
;;  DONE;
;;}")
;;
;;;; deib wants two qi's in separate registers or else they can be adjacent
;;;; in memory. DI mode will ensure two registers are available, but if we
;;;; want to allow memory as an operand we would need HI mode. There is no
;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
;;(define_insn "udivmoddiqi4_internal"
;;  [(set (match_operand:DI 0 "register_operand" "=r")
;;        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
;;                    (match_operand:QI 2 "general_operand" "g")] 0))]
;;  ""
;;  "deib %2,%0")
;;
;;(define_insn "udivmoddiqi4"
;;  [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
;;	(truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
;;		 (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
;;   (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
;;	(truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
;;  ""
;;  "deib %2,%0")

;;- Divide instructions.

(define_insn "divdf3"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=lm")
	(div:DF (match_operand:DF 1 "general_operand" "0")
		(match_operand:DF 2 "general_operand" "lmF")))]
  "TARGET_32081"
  "divl %2,%0")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
	(div:SF (match_operand:SF 1 "general_operand" "0")
		(match_operand:SF 2 "general_operand" "fmF")))]
  "TARGET_32081"
  "divf %2,%0")

;; See note 1
(define_insn "divsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(div:SI (match_operand:SI 1 "general_operand" "0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "quod %2,%0")

(define_insn "divhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(div:HI (match_operand:HI 1 "general_operand" "0")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "quow %2,%0")

(define_insn "divqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(div:QI (match_operand:QI 1 "general_operand" "0")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "quob %2,%0")

;; Remainder instructions.

;; See note 1
(define_insn "modsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(mod:SI (match_operand:SI 1 "general_operand" "0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "remd %2,%0")

(define_insn "modhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(mod:HI (match_operand:HI 1 "general_operand" "0")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "remw %2,%0")

(define_insn "modqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(mod:QI (match_operand:QI 1 "general_operand" "0")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "remb %2,%0")


;;- Logical Instructions: AND

;; See note 1
(define_insn "andsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(and:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
	{
	  if (INTVAL (operands[2]) == 0xffffff00)
	    return \"movqb %$0,%0\";
	  else
	    {
	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
	      return \"andb %2,%0\";
	    }
	}
      if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
        {
	  if (INTVAL (operands[2]) == 0xffff0000)
	    return \"movqw %$0,%0\";
	  else
	    {
	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
	      return \"andw %2,%0\";
	    }
	}
    }
  return \"andd %2,%0\";
}")

(define_insn "andhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(and:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
    {
      if (INTVAL (operands[2]) == 0xffffff00)
	return \"movqb %$0,%0\";
      else
	{
	  operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
	  return \"andb %2,%0\";
	}
    }
  return \"andw %2,%0\";
}")

(define_insn "andqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(and:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "andb %2,%0")

;; See note 1
(define_insn "*bicsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
		(match_operand:SI 2 "general_operand" "0")))]
  ""
  "bicd %1,%0")

(define_insn "*bichi"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
		(match_operand:HI 2 "general_operand" "0")))]
  ""
  "bicw %1,%0")

(define_insn "*bicqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
		(match_operand:QI 2 "general_operand" "0")))]
  ""
  "bicb %1,%0")

;;- Bit set instructions.

;; See note 1
(define_insn "iorsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(ior:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT) {
    if ((INTVAL (operands[2]) & 0xffffff00) == 0)
      return \"orb %2,%0\";
    if ((INTVAL (operands[2]) & 0xffff0000) == 0)
      return \"orw %2,%0\";
  }
  return \"ord %2,%0\";
}")

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(ior:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE(operands[2]) == CONST_INT &&
      (INTVAL(operands[2]) & 0xffffff00) == 0)
    return \"orb %2,%0\";
  return \"orw %2,%0\";
}")

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(ior:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "orb %2,%0")

;;- xor instructions.

;; See note 1
(define_insn "xorsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(xor:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT) {
    if ((INTVAL (operands[2]) & 0xffffff00) == 0)
      return \"xorb %2,%0\";
    if ((INTVAL (operands[2]) & 0xffff0000) == 0)
      return \"xorw %2,%0\";
  }
  return \"xord %2,%0\";
}")

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(xor:HI (match_operand:HI 1 "general_operand" "%0")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "*
{
  if (GET_CODE(operands[2]) == CONST_INT &&
      (INTVAL(operands[2]) & 0xffffff00) == 0)
    return \"xorb %2,%0\";
  return \"xorw %2,%0\";
}")

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(xor:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "xorb %2,%0")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=lm<")
	(neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
  "TARGET_32081"
  "negl %1,%0")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=fm<")
	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
  "TARGET_32081"
  "negf %1,%0")

(define_insn "negdi2"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
	(neg:DI (match_operand:DI 1 "nonimmediate_operand" "ro")))]
  ""
  "*
{
  rtx low[2], high[2], xops[4];
  split_di (operands, 2, low, high);
  xops[0] = low[0];
  xops[1] = high[0];
  xops[2] = low[1];
  xops[3] = high[1];

  if (rtx_equal_p (operands[0], operands[1]))
    {
      output_asm_insn (\"negd %3,%1\", xops);
      output_asm_insn (\"negd %2,%0\", xops);
      output_asm_insn (\"subcd %$0,%1\", xops);
    }
  else
    {
      output_asm_insn (\"negd %2,%0\", xops);
      output_asm_insn (\"movqd %$0,%1\", xops);
      output_asm_insn (\"subcd %3,%1\", xops);
    }
  return \"\"; 
}")

;; See note 1
(define_insn "negsi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "negd %1,%0")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "negw %1,%0")

(define_insn "negqi2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "negb %1,%0")

;; See note 1
(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
	(not:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "comd %1,%0")

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
	(not:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "comw %1,%0")

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
	(not:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "comb %1,%0")

;; arithmetic left and right shift operations
;; on the 32532 we will always use lshd for arithmetic left shifts,
;; because it is three times faster.  Broken programs which
;; use negative shift counts are probably broken differently
;; than elsewhere.

;; alternative 0 never matches on the 32532
;; See note 1
(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
	(ashift:SI (match_operand:SI 1 "general_operand" "r,0")
		   (match_operand:SI 2 "general_operand" "I,g")))]
  ""
  "*
{ if (TARGET_32532)
    return \"lshd %2,%0\";
  else
    return output_shift_insn (operands);
}")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
	(ashift:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) == 1)
	return \"addw %0,%0\";
      else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
	return \"addw %0,%0\;addw %0,%0\";
    }
  if (TARGET_32532)
    return \"lshw %2,%0\";
  else
    return \"ashw %2,%0\";
}")

(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
	(ashift:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) == 1)
	return \"addb %0,%0\";
      else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
	return \"addb %0,%0\;addb %0,%0\";
    }
  if (TARGET_32532)
    return \"lshb %2,%0\";
  else
    return \"ashb %2,%0\";
}")

;; Arithmetic right shift on the 32k works by negating the shift count.
(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
		     (match_operand:SI 2 "general_operand" "g")))]
  ""