seller.map.qmsg

自动售货机的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 23 14:56:00 2008 " "Info: Processing started: Sun Nov 23 14:56:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seller -c seller " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seller -c seller" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seller.v" { { "Info" "ISGN_ENTITY_NAME" "1 seller " "Info: Found entity 1: seller" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seller seller:inst " "Info: Elaborating entity \"seller\" for hierarchy \"seller:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 48 552 712 176 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "seller.v(111) " "Info (10264): Verilog HDL Case Statement information at seller.v(111): all case item expressions in this case statement are onehot" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 111 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Reset_Delay.v 1 1 " "Warning: Using design file Reset_Delay.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "E:/program/de1_fsm/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:inst2 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:inst2\"" {  } { { "Block1.bdf" "inst2" { Schematic "E:/program/de1_fsm/Block1.bdf" { { -32 360 480 64 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "debounce.v 1 1 " "Warning: Using design file debounce.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 debounce " "Info: Found entity 1: debounce" {  } { { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce debounce:inst3 " "Info: Elaborating entity \"debounce\" for hierarchy \"debounce:inst3\"" {  } { { "Block1.bdf" "inst3" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 368 352 640 464 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "std_div.v 1 1 " "Warning: Using design file std_div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 std_div " "Info: Found entity 1: std_div" {  } { { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "std_div std_div:inst1 " "Info: Elaborating entity \"std_div\" for hierarchy \"std_div:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 232 184 304 328 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "seller:inst\|fetch_alarm seller:inst\|sell_succeed " "Info: Duplicate register \"seller:inst\|fetch_alarm\" merged to single register \"seller:inst\|sell_succeed\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 10 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Block1\|seller:inst\|PS 5 " "Info: State machine \"\|Block1\|seller:inst\|PS\" contains 5 states" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Block1\|seller:inst\|PS " "Info: Selected Auto state machine encoding method for state machine \"\|Block1\|seller:inst\|PS\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Block1\|seller:inst\|PS " "Info: Encoding result for state machine \"\|Block1\|seller:inst\|PS\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "seller:inst\|PS.liangkuai " "Info: Encoded state bit \"seller:inst\|PS.liangkuai\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "seller:inst\|PS.yikuaiwu " "Info: Encoded state bit \"seller:inst\|PS.yikuaiwu\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "seller:inst\|PS.yikuai " "Info: Encoded state bit \"seller:inst\|PS.yikuai\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "seller:inst\|PS.wujiao " "Info: Encoded state bit \"seller:inst\|PS.wujiao\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "seller:inst\|PS.idle " "Info: Encoded state bit \"seller:inst\|PS.idle\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|seller:inst\|PS.idle 00000 " "Info: State \"\|Block1\|seller:inst\|PS.idle\" uses code string \"00000\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|seller:inst\|PS.yikuaiwu 01001 " "Info: State \"\|Block1\|seller:inst\|PS.yikuaiwu\" uses code string \"01001\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|seller:inst\|PS.yikuai 00101 " "Info: State \"\|Block1\|seller:inst\|PS.yikuai\" uses code string \"00101\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|seller:inst\|PS.wujiao 00011 " "Info: State \"\|Block1\|seller:inst\|PS.wujiao\" uses code string \"00011\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|seller:inst\|PS.liangkuai 10001 " "Info: State \"\|Block1\|seller:inst\|PS.liangkuai\" uses code string \"10001\"" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "99 " "Info: Implemented 99 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Allocated 126 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 23 14:56:03 2008 " "Info: Processing ended: Sun Nov 23 14:56:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}