seller.tan.qmsg

自动售货机的程序

{ "Info" "ITDB_TH_RESULT" "debounce:inst3\|dout1\[0\] key_in\[0\] clk_in -0.838 ns register " "Info: th for register \"debounce:inst3\|dout1\[0\]\" (data pin = \"key_in\[0\]\", clock pin = \"clk_in\") is -0.838 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 5.796 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 5.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_in 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 61 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 61; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.879 ns) 3.137 ns std_div:inst1\|clk_temp 3 REG LCFF_X25_Y3_N7 2 " "Info: 3: + IC(0.994 ns) + CELL(0.879 ns) = 3.137 ns; Loc. = LCFF_X25_Y3_N7; Fanout = 2; REG Node = 'std_div:inst1\|clk_temp'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.873 ns" { clk_in~clkctrl std_div:inst1|clk_temp } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.000 ns) 4.208 ns std_div:inst1\|clk_temp~clkctrl 4 COMB CLKCTRL_G15 6 " "Info: 4: + IC(1.071 ns) + CELL(0.000 ns) = 4.208 ns; Loc. = CLKCTRL_G15; Fanout = 6; COMB Node = 'std_div:inst1\|clk_temp~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.071 ns" { std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.602 ns) 5.796 ns debounce:inst3\|dout1\[0\] 5 REG LCFF_X43_Y14_N15 3 " "Info: 5: + IC(0.986 ns) + CELL(0.602 ns) = 5.796 ns; Loc. = LCFF_X43_Y14_N15; Fanout = 3; REG Node = 'debounce:inst3\|dout1\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[0] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 43.25 % ) " "Info: Total cell delay = 2.507 ns ( 43.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.289 ns ( 56.75 % ) " "Info: Total interconnect delay = 3.289 ns ( 56.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[0] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.920 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns key_in\[0\] 1 PIN PIN_R22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 1; PIN Node = 'key_in\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_in[0] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 408 40 208 424 "key_in\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.643 ns) + CELL(0.413 ns) 6.920 ns debounce:inst3\|dout1\[0\] 2 REG LCFF_X43_Y14_N15 3 " "Info: 2: + IC(5.643 ns) + CELL(0.413 ns) = 6.920 ns; Loc. = LCFF_X43_Y14_N15; Fanout = 3; REG Node = 'debounce:inst3\|dout1\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.056 ns" { key_in[0] debounce:inst3|dout1[0] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.277 ns ( 18.45 % ) " "Info: Total cell delay = 1.277 ns ( 18.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.643 ns ( 81.55 % ) " "Info: Total interconnect delay = 5.643 ns ( 81.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.920 ns" { key_in[0] debounce:inst3|dout1[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.920 ns" { key_in[0] key_in[0]~combout debounce:inst3|dout1[0] } { 0.000ns 0.000ns 5.643ns } { 0.000ns 0.864ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[0] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.920 ns" { key_in[0] debounce:inst3|dout1[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.920 ns" { key_in[0] key_in[0]~combout debounce:inst3|dout1[0] } { 0.000ns 0.000ns 5.643ns } { 0.000ns 0.864ns 0.413ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 23 14:56:52 2008 " "Info: Processing ended: Sun Nov 23 14:56:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}