seller.tan.qmsg

自动售货机的程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "std_div:inst1\|clk_temp " "Info: Detected ripple clock \"std_div:inst1\|clk_temp\" as buffer" {  } { { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "std_div:inst1\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register debounce:inst3\|dout2\[1\] register seller:inst\|PS.idle 175.13 MHz 5.71 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 175.13 MHz between source register \"debounce:inst3\|dout2\[1\]\" and destination register \"seller:inst\|PS.idle\" (period= 5.71 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.542 ns + Longest register register " "Info: + Longest register to register delay is 2.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns debounce:inst3\|dout2\[1\] 1 REG LCFF_X43_Y14_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y14_N3; Fanout = 3; REG Node = 'debounce:inst3\|dout2\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { debounce:inst3|dout2[1] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.521 ns) 0.899 ns seller:inst\|in_yikuai_reg~68 2 COMB LCCOMB_X43_Y14_N12 6 " "Info: 2: + IC(0.378 ns) + CELL(0.521 ns) = 0.899 ns; Loc. = LCCOMB_X43_Y14_N12; Fanout = 6; COMB Node = 'seller:inst\|in_yikuai_reg~68'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.899 ns" { debounce:inst3|dout2[1] seller:inst|in_yikuai_reg~68 } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.322 ns) 1.753 ns seller:inst\|Selector2~186 3 COMB LCCOMB_X43_Y14_N4 1 " "Info: 3: + IC(0.532 ns) + CELL(0.322 ns) = 1.753 ns; Loc. = LCCOMB_X43_Y14_N4; Fanout = 1; COMB Node = 'seller:inst\|Selector2~186'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.854 ns" { seller:inst|in_yikuai_reg~68 seller:inst|Selector2~186 } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.177 ns) 2.446 ns seller:inst\|Selector2~187 4 COMB LCCOMB_X42_Y14_N26 1 " "Info: 4: + IC(0.516 ns) + CELL(0.177 ns) = 2.446 ns; Loc. = LCCOMB_X42_Y14_N26; Fanout = 1; COMB Node = 'seller:inst\|Selector2~187'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.693 ns" { seller:inst|Selector2~186 seller:inst|Selector2~187 } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.542 ns seller:inst\|PS.idle 5 REG LCFF_X42_Y14_N27 3 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 2.542 ns; Loc. = LCFF_X42_Y14_N27; Fanout = 3; REG Node = 'seller:inst\|PS.idle'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { seller:inst|Selector2~187 seller:inst|PS.idle } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.116 ns ( 43.90 % ) " "Info: Total cell delay = 1.116 ns ( 43.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.426 ns ( 56.10 % ) " "Info: Total interconnect delay = 1.426 ns ( 56.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { debounce:inst3|dout2[1] seller:inst|in_yikuai_reg~68 seller:inst|Selector2~186 seller:inst|Selector2~187 seller:inst|PS.idle } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.542 ns" { debounce:inst3|dout2[1] seller:inst|in_yikuai_reg~68 seller:inst|Selector2~186 seller:inst|Selector2~187 seller:inst|PS.idle } { 0.000ns 0.378ns 0.532ns 0.516ns 0.000ns } { 0.000ns 0.521ns 0.322ns 0.177ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.929 ns - Smallest " "Info: - Smallest clock skew is -2.929 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.867 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_in 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 61 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 61; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.602 ns) 2.867 ns seller:inst\|PS.idle 3 REG LCFF_X42_Y14_N27 3 " "Info: 3: + IC(1.001 ns) + CELL(0.602 ns) = 2.867 ns; Loc. = LCFF_X42_Y14_N27; Fanout = 3; REG Node = 'seller:inst\|PS.idle'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.603 ns" { clk_in~clkctrl seller:inst|PS.idle } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.78 % ) " "Info: Total cell delay = 1.628 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.239 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.239 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { clk_in clk_in~clkctrl seller:inst|PS.idle } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { clk_in clk_in~combout clk_in~clkctrl seller:inst|PS.idle } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.796 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 5.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_in 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 61 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 61; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.879 ns) 3.137 ns std_div:inst1\|clk_temp 3 REG LCFF_X25_Y3_N7 2 " "Info: 3: + IC(0.994 ns) + CELL(0.879 ns) = 3.137 ns; Loc. = LCFF_X25_Y3_N7; Fanout = 2; REG Node = 'std_div:inst1\|clk_temp'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.873 ns" { clk_in~clkctrl std_div:inst1|clk_temp } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.000 ns) 4.208 ns std_div:inst1\|clk_temp~clkctrl 4 COMB CLKCTRL_G15 6 " "Info: 4: + IC(1.071 ns) + CELL(0.000 ns) = 4.208 ns; Loc. = CLKCTRL_G15; Fanout = 6; COMB Node = 'std_div:inst1\|clk_temp~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.071 ns" { std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.602 ns) 5.796 ns debounce:inst3\|dout2\[1\] 5 REG LCFF_X43_Y14_N3 3 " "Info: 5: + IC(0.986 ns) + CELL(0.602 ns) = 5.796 ns; Loc. = LCFF_X43_Y14_N3; Fanout = 3; REG Node = 'debounce:inst3\|dout2\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 43.25 % ) " "Info: Total cell delay = 2.507 ns ( 43.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.289 ns ( 56.75 % ) " "Info: Total interconnect delay = 3.289 ns ( 56.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { clk_in clk_in~clkctrl seller:inst|PS.idle } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { clk_in clk_in~combout clk_in~clkctrl seller:inst|PS.idle } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { debounce:inst3|dout2[1] seller:inst|in_yikuai_reg~68 seller:inst|Selector2~186 seller:inst|Selector2~187 seller:inst|PS.idle } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.542 ns" { debounce:inst3|dout2[1] seller:inst|in_yikuai_reg~68 seller:inst|Selector2~186 seller:inst|Selector2~187 seller:inst|PS.idle } { 0.000ns 0.378ns 0.532ns 0.516ns 0.000ns } { 0.000ns 0.521ns 0.322ns 0.177ns 0.096ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { clk_in clk_in~clkctrl seller:inst|PS.idle } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { clk_in clk_in~combout clk_in~clkctrl seller:inst|PS.idle } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout2[1] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "debounce:inst3\|dout1\[1\] key_in\[1\] clk_in 1.429 ns register " "Info: tsu for register \"debounce:inst3\|dout1\[1\]\" (data pin = \"key_in\[1\]\", clock pin = \"clk_in\") is 1.429 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.263 ns + Longest pin register " "Info: + Longest pin to register delay is 7.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns key_in\[1\] 1 PIN PIN_T22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_T22; Fanout = 1; PIN Node = 'key_in\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_in[1] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 408 40 208 424 "key_in\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.976 ns) + CELL(0.413 ns) 7.263 ns debounce:inst3\|dout1\[1\] 2 REG LCFF_X43_Y14_N13 3 " "Info: 2: + IC(5.976 ns) + CELL(0.413 ns) = 7.263 ns; Loc. = LCFF_X43_Y14_N13; Fanout = 3; REG Node = 'debounce:inst3\|dout1\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.389 ns" { key_in[1] debounce:inst3|dout1[1] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.287 ns ( 17.72 % ) " "Info: Total cell delay = 1.287 ns ( 17.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.976 ns ( 82.28 % ) " "Info: Total interconnect delay = 5.976 ns ( 82.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.263 ns" { key_in[1] debounce:inst3|dout1[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.263 ns" { key_in[1] key_in[1]~combout debounce:inst3|dout1[1] } { 0.000ns 0.000ns 5.976ns } { 0.000ns 0.874ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 5.796 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 5.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_in 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 61 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 61; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.879 ns) 3.137 ns std_div:inst1\|clk_temp 3 REG LCFF_X25_Y3_N7 2 " "Info: 3: + IC(0.994 ns) + CELL(0.879 ns) = 3.137 ns; Loc. = LCFF_X25_Y3_N7; Fanout = 2; REG Node = 'std_div:inst1\|clk_temp'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.873 ns" { clk_in~clkctrl std_div:inst1|clk_temp } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.000 ns) 4.208 ns std_div:inst1\|clk_temp~clkctrl 4 COMB CLKCTRL_G15 6 " "Info: 4: + IC(1.071 ns) + CELL(0.000 ns) = 4.208 ns; Loc. = CLKCTRL_G15; Fanout = 6; COMB Node = 'std_div:inst1\|clk_temp~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.071 ns" { std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl } "NODE_NAME" } } { "std_div.v" "" { Text "E:/program/de1_fsm/std_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.602 ns) 5.796 ns debounce:inst3\|dout1\[1\] 5 REG LCFF_X43_Y14_N13 3 " "Info: 5: + IC(0.986 ns) + CELL(0.602 ns) = 5.796 ns; Loc. = LCFF_X43_Y14_N13; Fanout = 3; REG Node = 'debounce:inst3\|dout1\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[1] } "NODE_NAME" } } { "debounce.v" "" { Text "E:/program/de1_fsm/debounce.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 43.25 % ) " "Info: Total cell delay = 2.507 ns ( 43.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.289 ns ( 56.75 % ) " "Info: Total interconnect delay = 3.289 ns ( 56.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[1] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.263 ns" { key_in[1] debounce:inst3|dout1[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.263 ns" { key_in[1] key_in[1]~combout debounce:inst3|dout1[1] } { 0.000ns 0.000ns 5.976ns } { 0.000ns 0.874ns 0.413ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.796 ns" { clk_in clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.796 ns" { clk_in clk_in~combout clk_in~clkctrl std_div:inst1|clk_temp std_div:inst1|clk_temp~clkctrl debounce:inst3|dout1[1] } { 0.000ns 0.000ns 0.238ns 0.994ns 1.071ns 0.986ns } { 0.000ns 1.026ns 0.000ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in sell seller:inst\|sell_succeed 7.822 ns register " "Info: tco from clock \"clk_in\" to destination pin \"sell\" through register \"seller:inst\|sell_succeed\" is 7.822 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.868 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk_in 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 61 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 61; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 56 224 88 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns seller:inst\|sell_succeed 3 REG LCFF_X44_Y14_N25 2 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X44_Y14_N25; Fanout = 2; REG Node = 'seller:inst\|sell_succeed'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk_in~clkctrl seller:inst|sell_succeed } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk_in clk_in~clkctrl seller:inst|sell_succeed } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk_in clk_in~combout clk_in~clkctrl seller:inst|sell_succeed } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.677 ns + Longest register pin " "Info: + Longest register to pin delay is 4.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seller:inst\|sell_succeed 1 REG LCFF_X44_Y14_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y14_N25; Fanout = 2; REG Node = 'seller:inst\|sell_succeed'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { seller:inst|sell_succeed } "NODE_NAME" } } { "seller.v" "" { Text "E:/program/de1_fsm/seller.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.807 ns) + CELL(2.870 ns) 4.677 ns sell 2 PIN PIN_Y21 0 " "Info: 2: + IC(1.807 ns) + CELL(2.870 ns) = 4.677 ns; Loc. = PIN_Y21; Fanout = 0; PIN Node = 'sell'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.677 ns" { seller:inst|sell_succeed sell } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/program/de1_fsm/Block1.bdf" { { 72 752 928 88 "sell" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.870 ns ( 61.36 % ) " "Info: Total cell delay = 2.870 ns ( 61.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.807 ns ( 38.64 % ) " "Info: Total interconnect delay = 1.807 ns ( 38.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.677 ns" { seller:inst|sell_succeed sell } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.677 ns" { seller:inst|sell_succeed sell } { 0.000ns 1.807ns } { 0.000ns 2.870ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk_in clk_in~clkctrl seller:inst|sell_succeed } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk_in clk_in~combout clk_in~clkctrl seller:inst|sell_succeed } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.677 ns" { seller:inst|sell_succeed sell } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.677 ns" { seller:inst|sell_succeed sell } { 0.000ns 1.807ns } { 0.000ns 2.870ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}